標(biāo)題: 關(guān)于ARMv8的AARCH架構(gòu)的neon指令使用 [打印本頁(yè)]
作者: cessi    時(shí)間: 2018-1-20 12:05
標(biāo)題: 關(guān)于ARMv8的AARCH架構(gòu)的neon指令使用
新版ARMv8架構(gòu)出現(xiàn)了ldn，和stn指令，分別是從內(nèi)存中載入和存儲(chǔ)，但是小弟關(guān)于n的作用不是很理解，希望有大神可以解答。附上st1和st4指令的說(shuō)明。ST1 (vector, multiple structures)
Store multiple 1-element structures from one, two three or four registers.
Syntax
ST1  { Vt.T }, [Xn|SP]    ; One registerST1  { Vt.T, Vt2.T }, [Xn|SP]    ; Two registersST1  { Vt.T, Vt2.T, Vt3.T }, [Xn|SP]    ; Three registersST1  { Vt.T, Vt2.T, Vt3.T, Vt4.T }, [Xn|SP]    ; Four registersST1  { Vt.T }, [Xn|SP], imm    ; One register, immediate offset, Post-indexST1  { Vt.T }, [Xn|SP], Xm    ; One register, register offset, Post-indexST1  { Vt.T, Vt2.T }, [Xn|SP], imm    ; Two registers, immediate offset, Post-indexST1  { Vt.T, Vt2.T }, [Xn|SP], Xm    ; Two registers, register offset, Post-indexST1  { Vt.T, Vt2.T, Vt3.T }, [Xn|SP], imm    ; Three registers, immediate offset, Post-indexST1  { Vt.T, Vt2.T, Vt3.T }, [Xn|SP], Xm    ; Three registers, register offset, Post-indexST1  { Vt.T, Vt2.T, Vt3.T, Vt4.T }, [Xn|SP], imm    ; Four registers, immediate offset, Post-indexST1  { Vt.T, Vt2.T, Vt3.T, Vt4.T }, [Xn|SP], Xm    ; Four registers, register offset, Post-index
Where:
Vt
Is the name of the first or only SIMD and FP register to be transferred, in the range 0 to 31.

Vt2
Is the name of the second SIMD and FP register to be transferred.

Vt3
Is the name of the third SIMD and FP register to be transferred.

Vt4
Is the name of the fourth SIMD and FP register to be transferred.

imm
Is the post-index immediate offset:
One register, immediate offset
Can be one of #8 or #16.

Two registers, immediate offset
Can be one of #16 or #32.

Three registers, immediate offset
Can be one of #24 or #48.

Four registers, immediate offset
Can be one of #32 or #64.



Xm
Is the 64-bit name of the general-purpose post-index register, excluding XZR, in the range 0 to 31.

T
Is an arrangement specifier, and can be one of the values shown in Usage.

Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer, in the range 0 to 31.




Note
Vt, Vt2, Vt3, and Vt4 must be consecutive registers. The next consecutive register after V31 is V0.


Usage
The following table shows valid specifier combinations:
Table 182. ST1 (One register, immediate offset) specifier combinations
[td]
T    imm
8B
   
#8
16B
   
#16
4H
   
#8
8H
   
#16
2S
   
#8
4S
   
#16
1D
   
#8
2D
   
#16



Table 183. ST1 (Two registers, immediate offset) specifier combinations
[td]
T    imm
8B
   
#16
16B
   
#32
4H
   
#16
8H
   
#32
2S
   
#16
4S
   
#32
1D
   
#16
2D
   
#32



Table 184. ST1 (Three registers, immediate offset) specifier combinations
[td]
T    imm
8B
   
#24
16B
   
#48
4H
   
#24
8H
   
#48
2S
   
#24
4S
   
#48
1D
   
#24
2D
   
#48



Table 185. ST1 (Four registers, immediate offset) specifier combinations
[td]
T    imm
8B
   
#32
16B
   
#64
4H
   
#32
8H
   
#64
2S
   
#32
4S
   
#64
1D
   
#32
2D
   
#64






ST1 (vector, single structure)
Store single 1-element structure from one lane of one register.
SyntaxST1  { Vt.B }[index], [Xn|SP]    ; 8-bitST1  { Vt.H }[index], [Xn|SP]    ; 16-bitST1  { Vt.S }[index], [Xn|SP]    ; 32-bitST1  { Vt.D }[index], [Xn|SP]    ; 64-bitST1  { Vt.B }[index], [Xn|SP], #1    ; 8-bit, immediate offset, Post-indexST1  { Vt.B }[index], [Xn|SP], Xm    ; 8-bit, register offset, Post-indexST1  { Vt.H }[index], [Xn|SP], #2    ; 16-bit, immediate offset, Post-indexST1  { Vt.H }[index], [Xn|SP], Xm    ; 16-bit, register offset, Post-indexST1  { Vt.S }[index], [Xn|SP], #4    ; 32-bit, immediate offset, Post-indexST1  { Vt.S }[index], [Xn|SP], Xm    ; 32-bit, register offset, Post-indexST1  { Vt.D }[index], [Xn|SP], #8    ; 64-bit, immediate offset, Post-indexST1  { Vt.D }[index], [Xn|SP], Xm    ; 64-bit, register offset, Post-index
Where:
Vt
Is the name of the first or only SIMD and FP register to be transferred, in the range 0 to 31.

index
The value depends on the instruction variant:
8-bit
Is the element index, in the range 0 to 15.

16-bit
Is the element index, in the range 0 to 7.

32-bit
Is the element index, in the range 0 to 3.

64-bit
Is the element index, and can be either 0 or 1.



Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer, in the range 0 to 31.

Xm
Is the 64-bit name of the general-purpose post-index register, excluding XZR, in the range 0 to 31.




See alsoReference

    A64 SIMD scalar instructions in alphabetical order.
    A64 SIMD vector instructions in alphabetical order.









ST4 (vector, multiple structures)
Store multiple 4-element structures from four registers.
Syntax
ST4  { Vt.T, Vt2.T, Vt3.T, Vt4.T }, [Xn|SP]ST4  { Vt.T, Vt2.T, Vt3.T, Vt4.T }, [Xn|SP], immST4  { Vt.T, Vt2.T, Vt3.T, Vt4.T }, [Xn|SP], Xm
Where:
Vt
Is the name of the first or only SIMD and FP register to be transferred, in the range 0 to 31.

Vt2
Is the name of the second SIMD and FP register to be transferred.

Vt3
Is the name of the third SIMD and FP register to be transferred.

Vt4
Is the name of the fourth SIMD and FP register to be transferred.

imm
Is the post-index immediate offset, and can be either #32 or #64.

Xm
Is the 64-bit name of the general-purpose post-index register, excluding XZR, in the range 0 to 31.

T
Is an arrangement specifier, and can be one of 8B, 16B, 4H, 8H, 2S, 4S or 2D.

Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer, in the range 0 to 31.




Note
Vt, Vt2, Vt3, and Vt4 must be consecutive registers. The next consecutive register after V31 is V0.

作者: cessi    時(shí)間: 2018-3-26 16:31
有人了解嗎？



歡迎光臨 (http://www.torrancerestoration.com/bbs/) Powered by Discuz! X3.1