標(biāo)題: 交通燈verilog源碼-凌陽(yáng)FPGA實(shí)驗(yàn)程序 含分頻 [打印本頁(yè)]
作者: 站站長(zhǎng)    時(shí)間: 2018-3-31 22:55
標(biāo)題: 交通燈verilog源碼-凌陽(yáng)FPGA實(shí)驗(yàn)程序 含分頻
凌陽(yáng)FPGA實(shí)驗(yàn)程序，包含分頻，交通燈源碼

單片機(jī)源程序如下:
  1. module traffic(CLK,EN,LAMPA,LAMPB,ACOUNT,BCOUNT);
  2. output[7:0] ACOUNT,BCOUNT;
  3. output[2:0] LAMPA,LAMPB;//lampa[2],lampa[1],lamp[0]as the red,green,yellow
  4.                         //lampb[2],lampb[1],lamp[0]--red,green,yellow
  5. input CLK,EN;//clk and enable(high is efficient)
  6. reg[7:0] numa,numb;
  7. reg tempa,tempb;
  8. reg[2:0] counta,countb;
  9. reg[7:0] ared,ayellow,agreen,bred,byellow,bgreen;
  10. reg[2:0] LAMPA,LAMPB;

  12. always @(EN)
  13. if(!EN)
  14.           begin
  15. ared<=8'b01000101;         
  16. ayellow<=8'b00000101;         
  17. agreen<= 8'b01000000;        
  18. bred<=8'b01000101;
  19. byellow<=8'b00000101;        
  20. bgreen<=8'b01000000;
  21.           end
  22. assign  ACOUNT=numa;
  23. assign  BCOUNT=numb;

  25. always @(posedge CLK)
  26.   begin
  27. if(EN)
  28. begin
  29. if(!tempa)
  30. begin
  31. tempa<=1;
  32. case(counta)
  33. 0:  begin numa<=ared;                LAMPA<=3'b100; counta<=1; end
  34. 1:  begin numa<=agreen;                LAMPA<=3'b010; counta<=2; end
  35. 2:  begin numa<=ayellow;        LAMPA<=3'b001; counta<=0; end
  36. default:                        LAMPA<=3'b100;
  37. endcase
  38. end
  39. else  begin
  40. if(numa>1)  
  41. if(numa[3:0]==0) begin
  42. numa[3:0]<=4'b1001;
  43. numa[7:4]<=numa[7:4]-1;
  44. end
  45. else                 numa[3:0]<=numa[3:0]-1;
  46. if (numa==2)  tempa<=0;
  47. end
  48. end
  49. else         begin
  50. LAMPA<=3'b100;
  51. counta<=0;   tempa<=0;
  52. end
  53.   end

  55. always @(posedge CLK)
  56. begin
  57.   if (EN)
  58.    begin
  59.     if(!tempb)
  60.      begin
  61.      tempb<=1;
  62.      case (countb)
  63. 0:  begin numb<=bgreen;                LAMPB<=3'b010; countb<=1; end
  64. 1:  begin numb<=byellow;        LAMPB<=3'b001; countb<=2; end
  65. 2:  begin numb<=bred;                LAMPB<=3'b100; countb<=0; end
  66. default:                        LAMPB<=3'b010;
  67.      endcase
  68.      end
  69.     else
  70.      begin
  71.       if(numb>1)
  72.        if(!numb[3:0])         begin
  73. numb[3:0]<=9;
  74. numb[7:4]<=numb[7:4]-1;
  75. end
  76. else          numb[3:0]<=numb[3:0]-1;
  77. if(numb==2)  tempb<=0;
  78.     end
  79.    end
  80. else          begin
  81. LAMPB<=3'b010;
  82. tempb<=0;   countb<=0;
  83. end
  84.   end
  85. endmodule
復(fù)制代碼


交通燈Verilog.zip

1.36 MB, 下載次數(shù): 31, 下載積分: 黑幣 -5





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