標題: EDA時鐘頂層設(shè)計VHDL源碼 [打印本頁]
作者: zysjj    時間: 2018-4-29 21:39
標題: EDA時鐘頂層設(shè)計VHDL源碼
EDA時鐘的頂層設(shè)計部分


VHDL源碼如下:
  1. // Copyright (C) 1991-2011 Altera Corporation
  2. // Your use of Altera Corporation's design tools, logic functions
  3. // and other software and tools, and its AMPP partner logic
  4. // functions, and any output files from any of the foregoing
  5. // (including device programming or simulation files), and any
  6. // associated documentation or information are expressly subject
  7. // to the terms and conditions of the Altera Program License
  8. // Subscription Agreement, Altera MegaCore Function License
  9. // Agreement, or other applicable license agreement, including,
  10. // without limitation, that your use is for the sole purpose of
  11. // programming logic devices manufactured by Altera and sold by
  12. // Altera or its authorized distributors.  Please refer to the
  13. // applicable agreement for further details.

  15. // PROGRAM                "Quartus II"
  16. // VERSION                "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version"
  17. // CREATED                "Sun Apr 16 10:29:37 2017"

  19. module dingceng(
  20.         clk,
  21.         reset,
  22.         set,
  23.         up,
  24.         d_col,
  25.         d_out
  26. );


  29. input wire        clk;
  30. input wire        reset;
  31. input wire        set;
  32. input wire        up;
  33. output wire        [7:0] d_col;
  34. output wire        [7:0] d_out;

  36. wire        h_set;
  37. wire        key_clk;
  38. wire        m_set;
  39. wire        s_clk;
  40. wire        s_set;
  41. wire        scan_clk;
  42. wire        set_en;
  43. wire        up_en;
  44. wire        [7:0] SYNTHESIZED_WIRE_0;
  45. wire        [7:0] SYNTHESIZED_WIRE_1;
  46. wire        [7:0] SYNTHESIZED_WIRE_2;





  52. Clock_cnt        b2v_inst(
  53.         .clk(clk),
  54.         .h_set(h_set),
  55.         .m_set(m_set),
  56.         .s_set(s_set),
  57.         .up_en(up_en),
  58.         .rst_n(reset),
  59.         .s_clk(s_clk),
  60.         .h_data(SYNTHESIZED_WIRE_0),
  61.         .m_data(SYNTHESIZED_WIRE_1),
  62.         .s_data(SYNTHESIZED_WIRE_2));


  65. Clock_ctl        b2v_inst1(
  66.         .clk(clk),
  67.         .rst_n(reset),
  68.         .set_en(set_en),
  69.         .h_set(h_set),
  70.         .m_set(m_set),
  71.         .s_set(s_set));
  72.         defparam        b2v_inst1.hour_set = 2'b01;
  73.         defparam        b2v_inst1.minute_set = 2'b10;
  74.         defparam        b2v_inst1.normal = 2'b00;
  75.         defparam        b2v_inst1.second_set = 2'b11;


  78. Key_ctl        b2v_inst2(
  79.         .set(set),
  80.         .rst_n(reset),
  81.         .clk(clk),
  82.         .key_clk(key_clk),
  83.         .set_en(set_en));


  86. up        b2v_inst3(
  87.         .up(up),
  88.         .rst_n(reset),
  89.         .clk(clk),
  90.         .key_clk(key_clk),
  91.         .up_en(up_en));


  94. Freq_div        b2v_inst4(
  95.         .clk(clk),
  96.         .rst_n(reset),
  97.         .scan_clk(scan_clk),
  98.         .key_clk(key_clk),
  99.         .s_clk(s_clk));


  102. Display        b2v_inst5(
  103.         .clk(clk),
  104.         .scan_clk(scan_clk),
  105.         .rst_n(reset),
  106.         .h_data(SYNTHESIZED_WIRE_0),
  107.         .m_data(SYNTHESIZED_WIRE_1),
  108.         .s_data(SYNTHESIZED_WIRE_2),
  109.         .d_col(d_col),
  110.         .d_out(d_out));


  113. endmodule
復(fù)制代碼

所有資料51hei提供下載:
dingceng.rar (5.9 MB, 下載次數(shù): 29)


作者: 小滄月兒    時間: 2019-12-21 10:34
太有用了，謝謝樓主



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