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2、所有程序設計代碼包括設計代碼、仿真代碼和約束文件。

FPGA源程序如下:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2018/06/20 21:42:40
// Design Name:
// Module Name: vote_7
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vote_7(
input clk,
input rst,
input[6:0]vote, //7位按鍵開關
output reg led, //小燈表示贊同or否決
output out1, //數(shù)碼管1輸出
output out2, //數(shù)碼管2輸出
output reg [6:0]state1, //數(shù)碼管1顯示贊同人數(shù)的總和
output reg [6:0]state2 //數(shù)碼管2顯示否決人數(shù)的總和
);
reg [2:0]sum; //計算贊同人數(shù)（開關）的總和
always @(posedge clk)
begin
if(!rst)
begin
sum<=0; //初始化sum等于0
end
else
sum<=vote[6]+vote[5]+vote[4]+vote[3]+vote[2]+vote[1]+vote[0]; //sum計人數(shù)（撥碼開關）的數(shù)量，求人數(shù)（撥碼開關）的總和
end
assign out1 = 1'b1; //給數(shù)碼管的兩個輸出out1、out2使能
assign out2 = 1'b1;
//片選一個數(shù)碼管顯示否決人數(shù)，將sum顯示的值顯示到數(shù)碼管1上，sum=0數(shù)碼管顯示0，sum=1數(shù)碼管顯示1，sum=2數(shù)碼管顯示2······
always@(negedge rst,posedge clk)
begin
if(!rst)
state1 <= 7'hff; //數(shù)碼管1初始化
else
begin
case(sum[2:0])
3'h0:state1 <= 7'b0111111;
3'h1:state1 <= 7'b0000110;
3'h2:state1 <= 7'b1011011;
3'h3:state1 <= 7'b1001111;
3'h4:state1 <= 7'b1100110;
3'h5:state1 <= 7'b1101101;
3'h6:state1 <= 7'b1111101;
3'h7:state1 <= 7'b0000111;
default :
state1 <= 7'b0111111;
endcase
end
end
//片選一個數(shù)碼管顯示否決人數(shù)，將sum顯示的值顯示到數(shù)碼管2上，sum=0數(shù)碼管顯示7，sum=1數(shù)碼管顯示6，sum=2數(shù)碼管顯示5······
always@(negedge rst,posedge clk)
begin
if(!rst)
state2 <= 7'hff;
else
begin
case(sum)
3'h0:state2 <= 7'b0000111;
3'h1:state2 <= 7'b1111101;
3'h2:state2 <= 7'b1101101;
3'h3:state2 <= 7'b1100110;
3'h4:state2 <= 7'b1001111;
3'h5:state2 <= 7'b1011011;
3'h6:state2 <= 7'b0000110;
3'h7:state2 <= 7'b0111111;
default :
state2 <= 7'h0000111;
endcase
end
end
//用小燈顯示通過和不通過，小燈亮，則通過；小燈滅則不通過。當sum值大于3時led小燈亮，否則小燈滅
always @(negedge rst,posedge clk)
begin
if(!rst)
begin
led<=0; //初始化小燈
end
else if(sum>=4)
led<=1;
else
led<=0;
end
endmodule

復制代碼

所有資料51hei提供下載:

vote_7.zip (2.25 KB, 下載次數(shù): 38)