ILI9486 supports MIPI DSI which can be enabled or disabled by external IM [4] pin. ILI9486 can be accessed
through one PHY lane module which communicates via two lines to a complementary part at the other side of
the lane interconnects. The communication can be separated two different levels between the MCU and ILI9486:
● Low level communication what is done on the interface level.
● High level communication what is done on the packet level.
ILI9486 uses data and clock lane differential pairs for DSI, The data lane (DATAP and DATAN) is used for data
communication and clock lane (CLKP and CLKN) is used to transmit the clock signal. The Mobile Industry
Processor Interface (MIPI) can be used for communication between the processor and DSI-compliant LCD
driver chip. The selection of this interface is done when IM [3:1] pins are high state (IOVCC level).
中景園電子3.5寸字庫SPI接口技術(shù)資料.zip
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