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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:33:30 09/26/2018
// Design Name:
// Module Name: count
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module count(
input clk_100Hz,
input rst,
input E,
output wire [3:0] s1,
output wire [3:0] s2,
output wire [3:0] s3,
output wire [3:0] s4,
output wire [3:0] s5,
output wire [3:0] s6
);
reg [3:0]i;
reg [3:0] count[1:6];
initial
begin
for(i=1;i<5;i=i+1)
begin
count[i]=4'b0000;
end
i=0;
end
always @ (posedge clk_100Hz)
begin
if(rst)
begin
for(i=1;i<7;i=i+1)
count[i]=4'b0000;
end
else if(!E)
begin
for(i=1;i<7;i=i+1)
count[i]=count[i];
end
else
begin
if(count[1]<10)
count[1]=count[1]+1;
if(count[1]==10)
begin
count[1]=0;
count[2]=count[2]+1;
end
if(count[2]==10)
begin
count[2]=0;
count[3]=count[3]+1;
end
if(count[3]==10)
begin
count[3]=0;
count[4]=count[4]+1;
end
if(count[4]==6)
begin
count[4]=0;
count[5]=count[5]+1;
end
if(count[5]==10)
begin
count[5]=0;
count[6]=count[6]+1;
end
if(count[6]==6)
begin
for(i=1;i<7;i=i+1)
count[i]=4'b0000;
end
end
end
assign s1 = count[1];
assign s2 = count[2];
assign s3 = count[3];
assign s4 = count[4];
assign s5 = count[5];
assign s6 = count[6];
endmodule

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