entity erxuanyi is
Port ( A, B, Sel : in std_logic;
Y : out std_logic);
end erxuanyi;
architecture Behavioral of erxuanyi is
begin
Y <= A when Sel = '0' else B;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sixuanyi is
Port ( A, B, C, D, Sel : in std_logic_vector(1 downto 0);
Y : out std_logic);
end sixuanyi;
-- 實(shí)現(xiàn)模塊
architecture Behavioral of sixuanyi is
-- 元件例化
component erxuanyi
Port ( A, B, Sel : in std_logic;
Y : out std_logic);
end component;
-- 信號(hào)定義
signal AB, CD : std_logic;
begin
-- 實(shí)例化二選一模塊
U1: erxuanyi port map (A => A(0), B => B(0), Sel => Sel(0), Y => AB);
U2: erxuanyi port map (A => C(0), B => D(0), Sel => Sel(0), Y => CD);
-- 連接選擇信號(hào)
U3: erxuanyi port map (A => AB, B => CD, Sel => Sel(1), Y => Y);
end Behavioral;
verilog語(yǔ)句的四選一結(jié)構(gòu)描述
module erxuanyi(
input A, B, Sel,
output Y
);
assign Y = (Sel == 1'b0) ? A : B;
endmodule
module sixuanyi(
input [1:0] A, B, C, D, Sel,
output Y
);