reg sync,data;
reg en_flag;
reg over_flag;
reg[79:0] data_send;
always @(posedge clk)
begin
if (reset)
begin
counter <= 0;
data <= 0;
data_send <= 80'h030255ae57aa65805501;
counter1 <= 0;
over_flag <= 1;
end
else
begin
if (en_flag)
begin
over_flag <= 0;
end
if (counter < 1 && counter1 < 10 &&!over_flag)
begin
sync <=1;
counter <= counter + 1;
end
else if (counter < 8 && counter1 < 10 &&!over_flag)
begin
sync <= 0;
temp = counter1*8 + counter - 1;
data <= data_send[temp];
counter <= counter + 1;
end
else if (counter >= 8 && counter1 < 10 &&!over_flag)
begin
temp = counter1*8 + counter - 1;
data <= data_send[temp];
counter <= 0;
counter1 <= counter1 + 1;
//data <= 0;
end
else if (counter1 >= 10 && !over_flag)
begin
counter1 <= 0;
over_flag <= 1;
end
end
end
reg start_flag;
reg[2:0] count2;
always @(posedge clk) //當(dāng)wr_en產(chǎn)生一個上升沿時，產(chǎn)生一個持續(xù)時間為3個sck時鐘周期的高脈沖。
begin
if(reset)
begin
start_flag <= 1;
count2 <= 3'd0;
en_flag <= 0;
end
else
begin
if (en)
begin
if (start_flag)
begin
if (count2 <= 2)
begin
en_flag <= 1;
count2 <= count2 + 3'd1;
end
else
begin
count2 <= 3'd0;
en_flag <= 0;
start_flag <= 0;
end
end
end
else
begin
start_flag <= 1;
en_flag <= 0;
end
end
end