算數(shù)運算時FPGA編程設(shè)計中常會用到的功能，其規(guī)則直接影響變成效果，調(diào)用use ieee.std_logic_unsigned.all;此程序包對不同的數(shù)據(jù)類型可以進行適當(dāng)?shù)乃銛?shù)運算：
1.對std_logic_vector()可進行相同位數(shù)的加減運算（被加數(shù)必須和輸出位數(shù)相同）；
2.對std_logic_vector()可進行相乘法運算（積的位數(shù)等于倆乘數(shù)位數(shù)之和）；
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity adder_n is
port(a,b:in std_logic_vector(4 downto 0);
c:in std_logic_vector(2 downto 0);
Sum1,sum2:out std_logic_vector(9 downto 0);
sum4,sum3 :out std_logic_vector(4 downto 0) );
end;
Architecture add of adder_n is
begin
Sum1<="00000"&a + b;
Sum2<=a * b;
sum3<=a - b;
sum4<=a + b;
end;
3.對Integer（整數(shù)）可以進行加、減、乘、除和取余運算；
Library ieee;
Useieee.std_logic_1164.all;
Useieee.std_logic_unsigned.all;
entity adder_n is
generic(n:integer:=4);----改變w的值可以改變運算寬度
port(a:in integerrange 0 to 4095;
dd,b:in integer range 0 to 255;
cin:in integer range 0 to 64;
Sum1,sum2:out integer range 0 to 4095;
ddd:out integer range 0 to 1023;
co1,co2:out integer range 0 to 1023);
end;
Architecture add of adder_n is
begin
Sum1<=a * b;---a,b一個可以是常數(shù)，如 Sum1<=2 * b
sum2<=a + b;
ddd<=a / b;---- 雖然是除，但實際為商 取整運算
co1<=a - dd;
co2<= a REM cin; --- 取余
end;