When the processor generates a memory access, the MMU:
1. Performs a lookup for a mapping for the requested virtual address and current ASID and
current world, Secure or Non-secure, in the relevant Instruction or Data MicroTLB.
2. If step 1 misses then a lookup for a mapping for the requested virtual address and current
ASID and current world, Secure or Non-secure, in the main TLB is performed.
If no global mapping, or mapping for the currently selected ASID, or no matching NSTID, for
the virtual address can be found in the TLBs then a translation table walk is automatically
performed by hardware, unless Page Table Walks are disabled by the PD0 or PD1 bits in the
TTB Control register, that cause the processor to return a Section Translation fault. See
Hardware page table translation on page 6-36.
If a matching TLB entry is found then the information it contains is used as follows:
1. The access permission bits and the domain are used to determine if the access is permitted.
If the access is not permitted the MMU signals a memory abort, otherwise the access is
enabled to proceed. Memory access control on page 6-11 describes how this is done.
2. The memory region attributes control the cache and write buffer, and determine if the
access is Secure or Non-secure cached, uncached, or device, and if it is shared, as Memory
region attributes on page 6-14 describes.
3. The physical address is used for any access to external or tightly coupled memory to
perform Tag matching for cache entries.
2. 址映射過程詳述
參考《ARM1176 JZF-S Technical Reference Manual》6.11節(jié)，Hardware page table translation
關(guān)于頁(yè)表：ARMv6的MMU進(jìn)行地址映射時(shí)涉及到兩種頁(yè)表，一級(jí)頁(yè)表（first level page table）和二級(jí)頁(yè)表(coarse page table)。
關(guān)于映射方式：映射方式有兩種，段映射和頁(yè)映射。段映射只用到一級(jí)頁(yè)表，頁(yè)映射用到一級(jí)頁(yè)表和二級(jí)頁(yè)表。
關(guān)于映射粒度：段映射的映射粒度有兩種，1M section和16M supersection；頁(yè)映射的映射粒度也有兩種，4K small page和64K large page。
硬件在做地址轉(zhuǎn)換時(shí)，如何知道當(dāng)前是什么映射方式以及映射粒度是多少呢？
In this model, the virtual address space is divided into two regions:
? 0x0 -> 1<<(32-N) that TTBR0 controls
? 1<<(32-N) -> 4GB that TTBR1 controls.
N的大小由TTBCR寄存器決定。0x0 -> 1<<(32-N)為用戶空間，由TTBR0控制，1<<(32-N) -> 4GB為內(nèi)核空間，由TTBR1控制。
N的大小與一級(jí)頁(yè)表大小的關(guān)系圖如下：