/*set the packet structure and the modulation type*/
//set the preamble length to 10bytes
SpiWriteRegister(0x34, 0x0C); //write 0x0A to the Preamble Length register
//set preamble detection threshold to 20bits
SpiWriteRegister(0x35, 0x2A); //write 0x2A to the Preamble Detection Control register
//Disable header bytes; set variable packet length (the length of the payload is defined by the
//received packet length field of the packet); set the synch word to two bytes long
SpiWriteRegister(0x33, 0x02); //write 0x02 to the Header Control2 register
//Set the sync word pattern to 0x2DD4
SpiWriteRegister(0x36, 0x2D); //write 0x2D to the Sync Word 3 register
SpiWriteRegister(0x37, 0xD4); //write 0xD4 to the Sync Word 2 register
//enable the TX & RX packet handler and CRC-16 (IBM) check
SpiWriteRegister(0x30, 0x8D); //write 0x8D to the Data Access Control register
//Disable the receive header filters
SpiWriteRegister(0x32, 0x00);
/*enable receiver chain*/
SpiWriteRegister(0x07, 0x05); //打開接收 //write 0x05 to the Operating Function Control 1 register
//Enable two interrupts:
// a) one which shows that a valid packet received: 'ipkval'
// b) second shows if the packet received with incorrect CRC: 'icrcerror'
SpiWriteRegister(0x05, 0x03); //打開 接收中斷 //write 0x03 to the Interrupt Enable 1 register
SpiWriteRegister(0x06, 0x00); //write 0x00 to the Interrupt Enable 2 register
//read interrupt status registers to release all pending interrupts
ItStatus1 = SpiReadRegister(0x03); //read the Interrupt Status1 register
ItStatus2 = SpiReadRegister(0x04);
}