標(biāo)題: 8位二進(jìn)制比較器的Verilog實(shí)現(xiàn) [打印本頁]
作者: 51黑黑黑    時(shí)間: 2016-2-23 01:17
標(biāo)題: 8位二進(jìn)制比較器的Verilog實(shí)現(xiàn)
題目：Use verilog to design a 8-bit comparer (only with atomic operator like "~, &, |, ^ and d=a?b:c)

代碼：
  
//逐位比較
  module comparer(dataa,datab,a_gt_b,a_it_b,a_eq_b);
  input [7:0] dataa,datab;
  output [7:0] a_gt_b,a_it_b,a_eq_b;
  wire [7:0] x_d;
  wire [7:0] y_d;
  wire a,b,eq;
  assign x_d[0]=(dataa[0] & datab[0])|((~dataa[0]) & (~datab[0]));
  assign x_d[1]=(dataa[1] & datab[1])|((~dataa[1]) & (~datab[1]));
  assign x_d[2]=(dataa[2] & datab[2])|((~dataa[2]) & (~datab[2]));
  assign x_d[3]=(dataa[3] & datab[3])|((~dataa[3]) & (~datab[3]));
  assign x_d[4]=(dataa[4] & datab[4])|((~dataa[4]) & (~datab[4]));
  assign x_d[5]=(dataa[5] & datab[5])|((~dataa[5]) & (~datab[5]));
  assign x_d[6]=(dataa[6] & datab[6])|((~dataa[6]) & (~datab[6]));
  assign x_d[7]=(dataa[7] & datab[7])|((~dataa[7]) & (~datab[7]));
  assign y_d[0]= x_d[7];
  assign y_d[1]= x_d[7] & x_d[6];
  assign y_d[2]= x_d[7] & x_d[6] & x_d[5];
  assign y_d[3]= x_d[7] & x_d[6] & x_d[5] & x_d[4];
  assign y_d[4]= x_d[7] & x_d[6] & x_d[5] & x_d[4] & x_d[3];
  assign y_d[5]= x_d[7] & x_d[6] & x_d[5] & x_d[4] & x_d[3] & x_d[2];
  assign y_d[6]= x_d[7] & x_d[6] & x_d[5] & x_d[4] & x_d[3] & x_d[2] & x_d[1];
  assign y_d[7]= x_d[7] & x_d[6] & x_d[5] & x_d[4] & x_d[3] & x_d[2] & x_d[1] & x_d[0];
  assign a=(dataa[7] & (~datab[7])) | (y_d[0] & dataa[6] & (~datab[6])) |(y_d[1] & dataa[5] & (~datab[5]))|
  (y_d[2] & dataa[4] & (~datab[4])) | (y_d[3] & dataa[3] & (~datab[3])) |(y_d[4] & dataa[2] & (~datab[2])) |
  (y_d[5] & dataa[1] & (~datab[1])) | (y_d[6] & dataa[0] & (~datab[0]));
  assign b=(datab[7] & (~dataa[7])) | (y_d[0] & datab[6] & (~dataa[6])) |(y_d[1] & datab[5] & (~dataa[5]))|
  (y_d[2] & datab[4] & (~dataa[4])) | (y_d[3] & datab[3] & (~dataa[3])) |(y_d[4] & datab[2] & (~dataa[2])) |
  (y_d[5] & datab[1] & (~dataa[1])) | (y_d[6] & datab[0] & (~dataa[0]));
  assign eq=y_d[7];
  assign a_gt_b=a?dataa:8'd0;
  assign a_it_b=b?datab:8'd0;
  assign a_eq_b=eq?dataa:8'd0;
  endmodule

仿真結(jié)果：



作者: 會(huì)心一笑    時(shí)間: 2017-12-22 20:41
請(qǐng)問這是不是測(cè)試程序？？
作者: 會(huì)心一笑    時(shí)間: 2017-12-22 20:42
請(qǐng)問這是不是測(cè)試程序？？



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