1.Found clock-sensitive change during active clock edge at time <time> on register "<name>"
原因：vector source file中時(shí)鐘敏感信號(hào)（如：數(shù)據(jù)，允許端，清零，同步加載等）在時(shí)鐘的邊緣同時(shí)變化。而時(shí)鐘敏感信號(hào)是不能在時(shí)鐘邊沿變化的。其后果為導(dǎo)致結(jié)果不正確。
措施：編輯vector source file
2.Verilog HDL assignment warning at <location>: truncated with size <number> to match size of target (<number>
原因:在HDL設(shè)計(jì)中對(duì)目標(biāo)的位數(shù)進(jìn)行了設(shè)定,如:reg[4:0] a;而默認(rèn)為32位,將位數(shù)裁定到合適的大小
措施:如果結(jié)果正確,無須加以修正,如果不想看到這個(gè)警告,可以改變?cè)O(shè)定的位數(shù)
3.All reachable assignments to data_out(10) assign '0', register removed by optimization
原因:經(jīng)過綜合器優(yōu)化后，輸出端口已經(jīng)不起作用了
4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
原因:第9腳，空或接地或接上了電源
措施:有時(shí)候定義了輸出端口，但輸出端直接賦‘0’，便會(huì)被接地，賦‘1’接電源。
如果你的設(shè)計(jì)中這些端口就是這樣用的，那便可以不理會(huì)這些warning
5.Found pins ing as undefined clocks and/or memory enables
原因:是你作為時(shí)鐘的PIN沒有約束信息�？梢詫�(duì)相應(yīng)的PIN做一下設(shè)定就行了。主要是指你的某些管腳在電路當(dāng)中起到了時(shí)鐘管腳的作用，比如flip-flop的clk管腳，而此管腳沒有時(shí)鐘約束，因此QuartusII把“clk”作為未定義的時(shí)鐘。
措施:如果clk不是時(shí)鐘，可以加“not clock”的約束；如果是，可以在clock setting當(dāng)中加入；在某些對(duì)時(shí)鐘要求不很高的情況下，可以忽略此警告或在這里修改:Assignments>Timing analysis settings...>Individual clocks...>...
6.Timing characteristics of device EPM570T144C5 are preliminary
原因:因?yàn)镸AXII 是比較新的元件在 QuartusII 中的時(shí)序并不是正式版的,要等 Service Pack
措施:只影響 Quartus 的 Waveform
7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
措施:將setting中的timing Requirements&Option-->More Timing Setting-->setting-->Enable Clock Latency中的on改成OFF
8.Found clock high time violation at 14.8 ns on register "|counter|lpm_counter:count1_rtl_0|dffs[11]"
原因:違反了steup/hold時(shí)間，應(yīng)該是后仿真，看看波形設(shè)置是否和時(shí)鐘沿符合steup/hold時(shí)間
措施:在中間加個(gè)寄存器可能可以解決問題
9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay
原因:時(shí)鐘抖動(dòng)大于數(shù)據(jù)延時(shí),當(dāng)時(shí)鐘很快，而if等類的層次過多就會(huì)出現(xiàn)這種問題,但這個(gè)問題多是在器件的最高頻率中才會(huì)出現(xiàn)
措施：setting-->timing Requirements&Options-->Default required fmax 改小一些，如改到50MHZ
10.Design contains <number> input pin(s) that do not drive logic
原因:輸入引腳沒有驅(qū)動(dòng)邏輯(驅(qū)動(dòng)其他引腳）,所有的輸入引腳需要有輸入邏輯
措施:如果這種情況是故意的,無須理會(huì),如果非故意,輸入邏輯驅(qū)動(dòng).
11.Warning：Found clock high time violation at 8.9ns on node 'TEST3.CLK'
原因：FF中輸入的PLS的保持時(shí)間過短
措施：在FF中設(shè)置較高的時(shí)鐘頻率
12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
原因:如果你用的 CPLD 只有一組全局時(shí)鐘時(shí)，用全局時(shí)鐘分頻產(chǎn)生的另一個(gè)時(shí)鐘在布線中當(dāng)作信號(hào)處理，不能保證低的時(shí)鐘歪斜(SKEW)。會(huì)造成在這個(gè)時(shí)鐘上工作的時(shí)序電路不可靠，甚至每次布線產(chǎn)生的問題都不一樣。
措施:如果用有兩組以上全局時(shí)鐘的 FPGA 芯片，可以把第二個(gè)全局時(shí)鐘作為另一個(gè)時(shí)鐘用，可以解決這個(gè)問題。
13.Critical Warning: Timing requirements were not met. See Report window for details.
原因：時(shí)序要求未滿足，
措施：雙擊Compilation Report-->Time Analyzer-->紅色部分（如clock setup:'clk'等）-->左鍵單擊list path,查看fmax的SLACK REPORT再根據(jù)提示解決,有可能是程序的算法問題
14.Can't achieve minimum setup and hold requirement <text> along <number> path(s). See Report window for details.
原因：時(shí)序分析發(fā)現(xiàn)一定數(shù)量的路徑違背了最小的建立和保持時(shí)間，與時(shí)鐘歪斜有關(guān),一般是由于多時(shí)鐘引起的
措施：利用Compilation Report-->Time Analyzer-->紅色部分（如clock hold:'clk'等），在slack中觀察是hold time為負(fù)值還是setup time 為負(fù)值，然后在：Assignment-->Assignment Editor-->To中增加時(shí)鐘名(from node finder)，Assignment Name中增加 多時(shí)鐘有關(guān)的Multicycle 和Multicycle Hold選項(xiàng)，如hold time為負(fù)，可使Multicycle hold的值>multicycle,如設(shè)為2和1。
15: Can't analyze file -- file E://quartusii/*/*.v is missing
原因：試圖編譯一個(gè)不存在的文件，該文件可能被改名或者刪除了
措施：不管他，沒什么影響
16.Warning: Can't find signal in vector source file for input pin |whole|clk10m
原因：因?yàn)槟愕牟ㄐ畏抡嫖募?vector source file ）中并沒有把所有的輸入
信號(hào)(input pin)加進(jìn)去，對(duì)于每一個(gè)輸入都需要有激勵(lì)源的
17.Error: Can't name logic scfifo0 of instance "inst" -- has same name as current design file
原因：模塊的名字和project的名字重名了
措施：把兩個(gè)名字之一改一下，一般改模塊的名字
18.Warning: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_fifo0
原因：模塊不是在本項(xiàng)目生成的，而是直接copy了別的項(xiàng)目的原理圖和源程序而生成的，而不是用QUARTUS將文件添加進(jìn)本項(xiàng)目
措施：無須理會(huì)，不影響使用
19.Timing characteristics of device <name> are preliminary
原因：目前版本的QuartusII只對(duì)該器件提供初步的時(shí)序特征分析
措施：如果堅(jiān)持用目前的器件，無須理會(huì)該警告。關(guān)于進(jìn)一步的時(shí)序特征分析會(huì)在后續(xù)版本的Quartus得到完善。
20.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
原因：用analyze_latches_as_synchronous_elements setting可以讓Quaruts II來分析同步鎖存，但目前的器件不支持這個(gè)特性
措施：無須理會(huì)。時(shí)序分析可能將鎖存器分析成回路。但并不一定分析正確。其后果可能會(huì)導(dǎo)致顯示提醒用戶：改變?cè)O(shè)計(jì)來消除鎖 存器
21.Warning:Found xx output pins without output pin load capacitance assignment（網(wǎng)友：gucheng82提供）
原因：沒有給輸出管教指定負(fù)載電容
措施：該功能用于估算TCO和功耗，可以不理會(huì)，也可以在Assignment Editor中為相應(yīng)的輸出管腳指定負(fù)載電容，以消除警告
22.Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
原因：使用了行波時(shí)鐘或門控時(shí)鐘，把觸發(fā)器的輸出當(dāng)時(shí)鐘用就會(huì)報(bào)行波時(shí)鐘，將組合邏輯的輸出當(dāng)時(shí)鐘用就會(huì)報(bào)門控時(shí)鐘
措施：不要把觸發(fā)器的輸出當(dāng)時(shí)鐘，不要將組合邏輯的輸出當(dāng)時(shí)鐘，如果本身如此設(shè)計(jì)，則無須理會(huì)該警告
23.Warning (10268): Verilog HDL information at lcd7106.v(63): Always Construct contains both blocking and non-blocking assignments
原因： 一個(gè)always模塊中同時(shí)有阻塞和非阻塞的賦值
１Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list
----沒把singal放到process（）中
2 Warning: Found pins ing as undefined clocks and/or memory enablesInfo: Assuming node CLK is an undefined clock
-=-----可能是說設(shè)計(jì)中產(chǎn)生的觸發(fā)器沒有使能端
3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout.
------信號(hào)類型設(shè)置不對(duì)，out當(dāng)作buffer來定義
4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen"
-------引用的例化元件未定義實(shí)體－－entity "clk_gen"
5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer
Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer
6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design.
7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
-----缺少敏感信號(hào)
8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register
9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND
10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" with clock skew larger than data delay. See Compilation Report for details.
11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" with clock skew larger than data delay. See Compilation Report for details.
12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with formal port "class" of mode "out"
------兩者不能連接起來
13 Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig[2]" in design.
------沒有編寫testbench文件，或者沒有編輯輸入變量的值 testbench里是元件申明和映射
14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component
---在相關(guān)的元件里沒有當(dāng)前文件所定義的類型
15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate" because signal does not hold its outside clock edge
16 Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]"
17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source file node.
---"temp[19]"被優(yōu)化掉了
18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND
19 Warning: Design contains 2 input pin(s) that do not drive logic
Warning: No output dependent on input pin "clk"
Warning: No output dependent on input pin "sign"
------輸出信號(hào)與輸入信號(hào)無關(guān)，
20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"
21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or"
22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared
-------連接表錯(cuò)誤，形參"alarm"賦值給實(shí)參，形參沒定義，可能是形參與實(shí)參的位置顛倒了，規(guī)定形參在實(shí)參之前。
23 Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors
�。�?yàn)榍耙粋�(gè)錯(cuò)誤而導(dǎo)致的錯(cuò)誤
24 Error: VHDL error at period_counter.vhd(38): type of identifier "alarm" does not agree with its usage as std_logic type
－－－－－－－－"alarm"的定義類型與使用的類型不一致
warning:
Info: Pin num[0] not assigned to an exact location on the device
num[0]管腳沒有在器件上非配一個(gè)準(zhǔn)確位置
解決方法：進(jìn)行管腳分配。
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
原因:是你作為時(shí)鐘的PIN沒有約束信息�？梢詫�(duì)相應(yīng)的PIN做一下設(shè)定就行了。主要是指你的某些管腳在電路當(dāng)中起到了時(shí)鐘管腳的作用，比如flip-flop的clk管腳，而此管腳沒有時(shí)鐘約束，因此QuartusII把“clk”作為未定義的時(shí)鐘。
措施:如果clk不是時(shí)鐘，可以加“not clock”的約束；如果是，可以在clock setting當(dāng)中加入；在某些對(duì)時(shí)鐘要求不很高的情況下，可以忽略此警告或在這里修改:Assignments>Timing analysis settings...>Individualclocks...>...
注意在Applies to node中只用選擇時(shí)鐘引腳一項(xiàng)即可，required fmax一般比所要求頻率高5%即可，無須太緊或太松。
25 Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement with conditions that test for the edges of multiple clocks
-------同一進(jìn)程中含有兩個(gè)或多個(gè)if(edge)條件，（一個(gè)進(jìn)程中之能有一個(gè)時(shí)鐘沿）
26 Error: Can't resolve multiple constant drivers for net "datain_reg[22]" at shift_reg.vhd(19)
27 can't infer register for signal "num[0]" because signal does not hold its outside clock edge
28Error: Can't elaborate top-level user hierarchy
29 Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32) ----------有兩個(gè)以上賦值語句，不能確定“cs_in”的值，
30 Warning: Ignored node in vector source file. Can't find corresponding node name "over" in design.
---------------在源文件中找不到對(duì)應(yīng)的節(jié)點(diǎn)“over”。
31 Error: Can't access JTAG chain
無法找到下載鏈
Warning (10541)的意思是設(shè)計(jì)中使用了一個(gè)未賦值的信號(hào)，并且沒有復(fù)位值，這樣該信號(hào)為無效值(確定但不可知)，被其他邏輯使用也許會(huì)導(dǎo)致錯(cuò)誤。
Warning (10036)不用管它，大概是說有個(gè)信號(hào)未被使用，這樣不會(huì)對(duì)邏輯產(chǎn)生任何影響，當(dāng)然也可以考慮刪除它。
Warning (10492)是很常見的，這個(gè)關(guān)系到編碼風(fēng)格問題。在process里作為被判斷信號(hào)(if或者case后面的)或者賦值語句右端信號(hào)通常應(yīng)該寫在process的敏感信號(hào)表里。有些eda工具不檢查這個(gè)，可能會(huì)導(dǎo)致仿真結(jié)果與綜合出來的電路不一致。實(shí)際上，綜合工具在綜合的時(shí)候會(huì)自動(dòng)把這類信號(hào)添加到敏感信號(hào)表里，但仿真工具不會(huì)，而是完全按照代碼體現(xiàn)的語意來仿真。
Reduced register ...這兩個(gè)應(yīng)該是說明eda工具所作的優(yōu)化，去掉了一些多余的D觸發(fā)器。
Output pins are stuck at VCC or GND 如果正是希望某些輸出被固定置高電平或低電平或者無所謂，就不用管它，否則請(qǐng)檢查代碼。
Design contains 1 input pin(s) that do not drive logic 這個(gè)也比較常見，eda工具會(huì)提醒設(shè)計(jì)中沒被用到的輸入，然而這經(jīng)常就是設(shè)計(jì)者的本意(不關(guān)心某些輸入)。
Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew 這就是說明門控時(shí)鐘帶來的扭曲
1.Found clock-sensitive change during active clock edge at time <time> on register "<name>"
原因：vector source file中時(shí)鐘敏感信號(hào)（如：數(shù)據(jù)，允許端，清零，同步加載等）在時(shí)鐘的邊緣同時(shí)變化。而時(shí)鐘敏感信號(hào)是
不能在時(shí)鐘邊沿變化的。其后果為導(dǎo)致結(jié)果不正確。
措施：編輯vector source file
2.Verilog HDL assignment warning at <location>: truncated value with size <number> to match size of target (<number>
原因:在HDL設(shè)計(jì)中對(duì)目標(biāo)的位數(shù)進(jìn)行了設(shè)定,如:reg[4:0] a;而默認(rèn)為32位,將位數(shù)裁定到合適的大小
措施:如果結(jié)果正確,無須加以修正,如果不想看到這個(gè)警告,可以改變?cè)O(shè)定的位數(shù)
3.All reachable assignments to data_out(10) assign '0', register removed by optimization
原因:經(jīng)過綜合器優(yōu)化后，輸出端口已經(jīng)不起作用了
4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
原因:第9腳，空或接地或接上了電源
措施:有時(shí)候定義了輸出端口，但輸出端直接賦‘0’，便會(huì)被接地，賦‘1’接電源。如果你的設(shè)計(jì)中這些端口就是這樣用的，那便可以不理會(huì)這些warning
5.Found pins functioning as undefined clocks and/or memory enables
原因:是你作為時(shí)鐘的PIN沒有約束信息�？梢詫�(duì)相應(yīng)的PIN做一下設(shè)定就行了。主要是指你的某些管腳在電路當(dāng)中起到了時(shí)鐘管腳的
作用，比如flip-flop的clk管腳，而此管腳沒有時(shí)鐘約束，因此QuartusII把“clk”作為未定義的時(shí)鐘。
措施:如果clk不是時(shí)鐘，可以加“not clock”的約束；如果是，可以在clock setting當(dāng)中加入；在某些對(duì)時(shí)鐘要求不很高的情況下，可以忽略此警告或在這里修改:Assignments>Timing analysis settings...>Individual clocks...>...
6.Timing characteristics of device EPM570T144C5 are preliminary
原因:因?yàn)镸AXII 是比較新的元件在 QuartusII 中的時(shí)序並不是正式版的,要等 Service Pack
措施:只影響 Quartus 的 Waveform
7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
措施:將setting中的timing Requirements&Option-->More Timing Setting-->setting-->Enable Clock Latency中的on改成OFF
8.Found clock high time violation at 14.8 ns on register "|counter|lpm_counter:count1_rtl_0|dffs[11]"
原因:違反了steup/hold時(shí)間，應(yīng)該是后仿真，看看波形設(shè)置是否和時(shí)鐘沿符合steup/hold時(shí)間
措施:在中間加個(gè)寄存器可能可以解決問題
9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay
原因:時(shí)鐘抖動(dòng)大于數(shù)據(jù)延時(shí),當(dāng)時(shí)鐘很快，而if等類的層次過多就會(huì)出現(xiàn)這種問題,但這個(gè)問題多是在器件的最高頻率中才會(huì)出現(xiàn)
措施：setting-->timing Requirements&Options-->Default required fmax 改小一些，如改到50MHZ
10.Design contains <number> input pin(s) that do not drive logic
原因:輸入引腳沒有驅(qū)動(dòng)邏輯(驅(qū)動(dòng)其他引腳）,所有的輸入引腳需要有輸入邏輯
措施:如果這種情況是故意的,無須理會(huì),如果非故意,輸入邏輯驅(qū)動(dòng).
11.Warning：Found clock high time violation at 8.9ns on node 'TEST3.CLK'
原因：FF中輸入的PLS的保持時(shí)間過短
措施：在FF中設(shè)置較高的時(shí)鐘頻率
12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
原因:如果你用的 CPLD 只有一組全局時(shí)鐘時(shí)，用全局時(shí)鐘分頻產(chǎn)生的另一個(gè)時(shí)鐘在布線中當(dāng)作信號(hào)處理，不能保證低的時(shí)鐘歪斜(SKEW)。會(huì)造成在這個(gè)時(shí)鐘上工作的時(shí)序電路不可靠，甚至每次布線產(chǎn)生的問題都不一樣。
措施:如果用有兩組以上全局時(shí)鐘的 FPGA 芯片，可以把第二個(gè)全局時(shí)鐘作為另一個(gè)時(shí)鐘用，可以解決這個(gè)問題。
第5條補(bǔ)充如下:
5.Found pins functioning as undefined clocks and/or memory enables
......可以忽略此警告 Assignments>Timing analysis settings...>Individual clocks...>... new Clock setting-->注意在Applies to node中只用選擇時(shí)鐘引腳一項(xiàng)即可，required fmax一般比所要求頻率高5%即可，無須太緊或太松。
增加第13條:
13.Critical Warning: Timing requirements were not met. See Report window for details.
原因：時(shí)序要求未滿足，
措施：雙擊Compilation Report-->Time Analyzer-->紅色部分（如clock setup:'clk'等）-->左鍵單擊list path,查看fmax的SLACK REPORT再根據(jù)提示解決,有可能是程序的算法問題或fmax設(shè)置問題
ps:大家如果有什么難解決的warning也可以發(fā)上來討論一下,如果有已經(jīng)解決的疑難warning解決方法,也可以一起分享經(jīng)驗(yàn).上面的情況如有錯(cuò)誤之處,歡迎拍磚
14.Can't achieve minimum setup and hold requirement <text> along <number> path(s). See Report window for details.
原因：時(shí)序分析發(fā)現(xiàn)一定數(shù)量的路徑違背了最小的建立和保持時(shí)間，與時(shí)鐘歪斜有關(guān),一般是由于多時(shí)鐘引起的
措施：利用Compilation Report-->Time Analyzer-->紅色部分（如clock hold:'clk'等），在slack中觀察是hold time為負(fù)值還是setup time 為負(fù)值，然后在：Assignment-->Assignment Editor-->To中增加時(shí)鐘名(from node finder)，Assignment Name中增加和多時(shí)鐘有關(guān)的Multicycle 和Multicycle Hold選項(xiàng)，如hold time為負(fù)，可使Multicycle hold的值>multicycle,如設(shè)為2和1。
15: Can't analyze file -- file E://quartusii/*/*.v is missing
原因：試圖編譯一個(gè)不存在的文件，該文件可能被改名或者刪除了措施：不管他，沒什么影響
16.Warning: Can't find signal in vector source file for input pin |whole|clk10m
原因：因?yàn)槟愕牟ㄐ畏抡嫖募?vector source file ）中并沒有把所有的輸入信號(hào)(input pin)加進(jìn)去， 對(duì)于每一個(gè)輸入都需要有激勵(lì)源的
17.Error: Can't name logic function scfifo0 of instance "inst" -- function has same name as current design file
原因：模塊的名字和project的名字重名了
措施：把兩個(gè)名字之一改一下，一般改模塊的名字
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