標(biāo)題:
我遇到的quartus錯(cuò)誤與警告
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作者:
電子黑
時(shí)間:
2016-6-29 14:45
標(biāo)題:
我遇到的quartus錯(cuò)誤與警告
1、Error: Can't continue timing simulation because delay annotation information for design is missing
這是因?yàn)槲磳?duì)工程進(jìn)行綜合編譯，無法仿真。
解決辦法：編譯一次
2、Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
CLK沒有定義成時(shí)鐘信號(hào)
解決辦法：pin lanner中將clk定義到晶振引腳或clk接到某個(gè)時(shí)鐘信號(hào)（可以使pll輸出）上
3、Warning: Converted tri-state buffer "init_module:j2|initial_control_module:u1|wr_data[0]" feeding internal logic into a wire
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