標(biāo)題: FPGA模十可逆計(jì)數(shù)器加到9不能直接跳到0 [打印本頁(yè)]

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作者: KUNGONG    時(shí)間: 2017-10-13 23:03
標(biāo)題: FPGA模十可逆計(jì)數(shù)器加到9不能直接跳到0
今天寫(xiě)了一個(gè)按鍵的模十可逆計(jì)數(shù)器，但是加到9不能直接跳到0，減到0不能直接跳到9，新手，求大佬幫忙解答下，小弟我定當(dāng)感激不盡。

module counter_10(in1,in2,out);
input in1,in2;
output [6:0] out;
reg [3:0] out1=0;
reg [3:0] out2=0;
reg [3:0] in=0;
reg [6:0] out=0;
always @(posedge in1)
begin
if(in1)
begin
if(out1>=1010)
out1=0;
else
out1=out1+1;
end
end
always @(posedge in2)
begin
if(in2)
begin
if(out2>=1010)
out2=0;
else
out2=out2-1;
end
end
always @(in)
begin
in<=out1+out2;
case(in)
  4'b0000:out=7'b0000001;
  4'b0001:out=7'b1001111;
  4'b0010:out=7'b0010010;
  4'b0011:out=7'b0000110;
  4'b0100:out=7'b1001100;
  4'b0101:out=7'b0100100;
  4'b0110:out=7'b1100000;
  4'b0111:out=7'b0001111;
  4'b1000:out=7'b0000000;
  4'b1001:out=7'b0001100;
  default:out=7'b1111111;
endcase
end
endmodule

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