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發(fā)布時間: 2019-10-10 00:47
正文摘要:寫規(guī)格書里面的 CMCON0或CMPON都下劃紅線 編譯失敗 寫CMCON沒有紅線編譯也失敗 現(xiàn)在是想用GP1做輸入 發(fā)現(xiàn)不行 GP3可以 |
1302798532 發(fā)表于 2019-10-11 10:15 已經知道為什么劃紅線了  |
| 有沒有朋友能試下這個程序你們有沒有GP0無上拉和CMCON0報錯的問題 或者有沒有用GP0做上拉輸入的程序我來試一下 |
本帖最后由 gravedigger 于 2019-10-12 10:43 編輯 1302798532 發(fā)表于 2019-10-11 10:15 頭文件沒有發(fā)現(xiàn)比較器 后面不用燒錄器供電GP1 就有上拉了 GP0還是沒有 #include<pic.h> #include <xc.h> #pragma config WDTE = OFF // Watchdog Timer (WDT disabled) #pragma config CP = OFF // Code Protect (Code protection off) #pragma config MCLRE = OFF // Master Clear Enable (GP3/MCLR pin fuction is digital I/O, MCLR internally tied to VDD) #define KEY GP1 //換成GP0沒上拉 要外接 #define LED GP2 void main() { TRISGPIO=0b00001011; OSCCAL=0b11111110; OPTION=0b00000111; // CMCON = 0; //CMCON0寫出來就下劃紅線 CMCON不紅線 編譯會出錯 GP0=GP1=GP2=0; while(1) { if(KEY==0) { LED=1; } else { LED=0; } } } 下面是頭文件 // Version 1.34 // Generated 16/02/2015 GMT /* * Copyright © 2015, Microchip Technology Inc. and its subsidiaries ("Microchip") * All rights reserved. * * This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip"). * * Redistribution and use in source and binary forms, with or without modification, are * permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * * 3. Microchip's name may not be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #ifndef _PIC10F202_H_ #define _PIC10F202_H_ /* * C Header file for the Microchip PIC Microcontroller * PIC10F202 * */ #ifndef __XC8 #warning Header file pic10f202.h included directly. Use #include <xc.h> instead. #endif /* * Register Definitions * */ // Register: INDF extern volatile unsigned char INDF @ 0x000; #ifndef _LIB_BUILD asm("INDF equ 00h"); #endif // bitfield definitions typedef union { struct { unsigned INDF :8; }; } INDFbits_t; extern volatile INDFbits_t INDFbits @ 0x000; // bitfield macros #define _INDF_INDF_POSN 0x0 #define _INDF_INDF_POSITION 0x0 #define _INDF_INDF_SIZE 0x8 #define _INDF_INDF_LENGTH 0x8 #define _INDF_INDF_MASK 0xFF // Register: TMR0 extern volatile unsigned char TMR0 @ 0x001; #ifndef _LIB_BUILD asm("TMR0 equ 01h"); #endif // bitfield definitions typedef union { struct { unsigned TMR0 :8; }; } TMR0bits_t; extern volatile TMR0bits_t TMR0bits @ 0x001; // bitfield macros #define _TMR0_TMR0_POSN 0x0 #define _TMR0_TMR0_POSITION 0x0 #define _TMR0_TMR0_SIZE 0x8 #define _TMR0_TMR0_LENGTH 0x8 #define _TMR0_TMR0_MASK 0xFF // Register: PCL extern volatile unsigned char PCL @ 0x002; #ifndef _LIB_BUILD asm("PCL equ 02h"); #endif // bitfield definitions typedef union { struct { unsigned PCL :8; }; } PCLbits_t; extern volatile PCLbits_t PCLbits @ 0x002; // bitfield macros #define _PCL_PCL_POSN 0x0 #define _PCL_PCL_POSITION 0x0 #define _PCL_PCL_SIZE 0x8 #define _PCL_PCL_LENGTH 0x8 #define _PCL_PCL_MASK 0xFF // Register: STATUS extern volatile unsigned char STATUS @ 0x003; #ifndef _LIB_BUILD asm("STATUS equ 03h"); #endif // bitfield definitions typedef union { struct { unsigned C :1; unsigned DC :1; unsigned Z :1; unsigned nPD :1; unsigned nTO :1; unsigned :2; unsigned GPWUF :1; }; struct { unsigned CARRY :1; }; struct { unsigned :2; unsigned ZERO :1; }; } STATUSbits_t; extern volatile STATUSbits_t STATUSbits @ 0x003; // bitfield macros #define _STATUS_C_POSN 0x0 #define _STATUS_C_POSITION 0x0 #define _STATUS_C_SIZE 0x1 #define _STATUS_C_LENGTH 0x1 #define _STATUS_C_MASK 0x1 #define _STATUS_DC_POSN 0x1 #define _STATUS_DC_POSITION 0x1 #define _STATUS_DC_SIZE 0x1 #define _STATUS_DC_LENGTH 0x1 #define _STATUS_DC_MASK 0x2 #define _STATUS_Z_POSN 0x2 #define _STATUS_Z_POSITION 0x2 #define _STATUS_Z_SIZE 0x1 #define _STATUS_Z_LENGTH 0x1 #define _STATUS_Z_MASK 0x4 #define _STATUS_nPD_POSN 0x3 #define _STATUS_nPD_POSITION 0x3 #define _STATUS_nPD_SIZE 0x1 #define _STATUS_nPD_LENGTH 0x1 #define _STATUS_nPD_MASK 0x8 #define _STATUS_nTO_POSN 0x4 #define _STATUS_nTO_POSITION 0x4 #define _STATUS_nTO_SIZE 0x1 #define _STATUS_nTO_LENGTH 0x1 #define _STATUS_nTO_MASK 0x10 #define _STATUS_GPWUF_POSN 0x7 #define _STATUS_GPWUF_POSITION 0x7 #define _STATUS_GPWUF_SIZE 0x1 #define _STATUS_GPWUF_LENGTH 0x1 #define _STATUS_GPWUF_MASK 0x80 #define _STATUS_CARRY_POSN 0x0 #define _STATUS_CARRY_POSITION 0x0 #define _STATUS_CARRY_SIZE 0x1 #define _STATUS_CARRY_LENGTH 0x1 #define _STATUS_CARRY_MASK 0x1 #define _STATUS_ZERO_POSN 0x2 #define _STATUS_ZERO_POSITION 0x2 #define _STATUS_ZERO_SIZE 0x1 #define _STATUS_ZERO_LENGTH 0x1 #define _STATUS_ZERO_MASK 0x4 // Register: FSR extern volatile unsigned char FSR @ 0x004; #ifndef _LIB_BUILD asm("FSR equ 04h"); #endif // bitfield definitions typedef union { struct { unsigned FSR :8; }; } FSRbits_t; extern volatile FSRbits_t FSRbits @ 0x004; // bitfield macros #define _FSR_FSR_POSN 0x0 #define _FSR_FSR_POSITION 0x0 #define _FSR_FSR_SIZE 0x8 #define _FSR_FSR_LENGTH 0x8 #define _FSR_FSR_MASK 0xFF // Register: OSCCAL extern volatile unsigned char OSCCAL @ 0x005; #ifndef _LIB_BUILD asm("OSCCAL equ 05h"); #endif // bitfield definitions typedef union { struct { unsigned FOSC4 :1; unsigned CAL :7; }; struct { unsigned :1; unsigned CAL0 :1; unsigned CAL1 :1; unsigned CAL2 :1; unsigned CAL3 :1; unsigned CAL4 :1; unsigned CAL5 :1; unsigned CAL6 :1; }; } OSCCALbits_t; extern volatile OSCCALbits_t OSCCALbits @ 0x005; // bitfield macros #define _OSCCAL_FOSC4_POSN 0x0 #define _OSCCAL_FOSC4_POSITION 0x0 #define _OSCCAL_FOSC4_SIZE 0x1 #define _OSCCAL_FOSC4_LENGTH 0x1 #define _OSCCAL_FOSC4_MASK 0x1 #define _OSCCAL_CAL_POSN 0x1 #define _OSCCAL_CAL_POSITION 0x1 #define _OSCCAL_CAL_SIZE 0x7 #define _OSCCAL_CAL_LENGTH 0x7 #define _OSCCAL_CAL_MASK 0xFE #define _OSCCAL_CAL0_POSN 0x1 #define _OSCCAL_CAL0_POSITION 0x1 #define _OSCCAL_CAL0_SIZE 0x1 #define _OSCCAL_CAL0_LENGTH 0x1 #define _OSCCAL_CAL0_MASK 0x2 #define _OSCCAL_CAL1_POSN 0x2 #define _OSCCAL_CAL1_POSITION 0x2 #define _OSCCAL_CAL1_SIZE 0x1 #define _OSCCAL_CAL1_LENGTH 0x1 #define _OSCCAL_CAL1_MASK 0x4 #define _OSCCAL_CAL2_POSN 0x3 #define _OSCCAL_CAL2_POSITION 0x3 #define _OSCCAL_CAL2_SIZE 0x1 #define _OSCCAL_CAL2_LENGTH 0x1 #define _OSCCAL_CAL2_MASK 0x8 #define _OSCCAL_CAL3_POSN 0x4 #define _OSCCAL_CAL3_POSITION 0x4 #define _OSCCAL_CAL3_SIZE 0x1 #define _OSCCAL_CAL3_LENGTH 0x1 #define _OSCCAL_CAL3_MASK 0x10 #define _OSCCAL_CAL4_POSN 0x5 #define _OSCCAL_CAL4_POSITION 0x5 #define _OSCCAL_CAL4_SIZE 0x1 #define _OSCCAL_CAL4_LENGTH 0x1 #define _OSCCAL_CAL4_MASK 0x20 #define _OSCCAL_CAL5_POSN 0x6 #define _OSCCAL_CAL5_POSITION 0x6 #define _OSCCAL_CAL5_SIZE 0x1 #define _OSCCAL_CAL5_LENGTH 0x1 #define _OSCCAL_CAL5_MASK 0x40 #define _OSCCAL_CAL6_POSN 0x7 #define _OSCCAL_CAL6_POSITION 0x7 #define _OSCCAL_CAL6_SIZE 0x1 #define _OSCCAL_CAL6_LENGTH 0x1 #define _OSCCAL_CAL6_MASK 0x80 // Register: GPIO extern volatile unsigned char GPIO @ 0x006; #ifndef _LIB_BUILD asm("GPIO equ 06h"); #endif // bitfield definitions typedef union { struct { unsigned GP0 :1; unsigned GP1 :1; unsigned GP2 :1; unsigned GP3 :1; }; } GPIObits_t; extern volatile GPIObits_t GPIObits @ 0x006; // bitfield macros #define _GPIO_GP0_POSN 0x0 #define _GPIO_GP0_POSITION 0x0 #define _GPIO_GP0_SIZE 0x1 #define _GPIO_GP0_LENGTH 0x1 #define _GPIO_GP0_MASK 0x1 #define _GPIO_GP1_POSN 0x1 #define _GPIO_GP1_POSITION 0x1 #define _GPIO_GP1_SIZE 0x1 #define _GPIO_GP1_LENGTH 0x1 #define _GPIO_GP1_MASK 0x2 #define _GPIO_GP2_POSN 0x2 #define _GPIO_GP2_POSITION 0x2 #define _GPIO_GP2_SIZE 0x1 #define _GPIO_GP2_LENGTH 0x1 #define _GPIO_GP2_MASK 0x4 #define _GPIO_GP3_POSN 0x3 #define _GPIO_GP3_POSITION 0x3 #define _GPIO_GP3_SIZE 0x1 #define _GPIO_GP3_LENGTH 0x1 #define _GPIO_GP3_MASK 0x8 // Register: OPTION extern volatile __control unsigned char OPTION @ 0x000; // Register: TRIS extern volatile __control unsigned char TRIS @ 0x006; // Register: TRISGPIO extern volatile __control unsigned char TRISGPIO @ 0x006; /* * OPTION bits * */ #define PS 0x7 #define PSA 0x8 #define T0SE 0x10 #define T0CS 0x20 #define nGPPU 0x40 #define nGPWU 0x80 #define PS0 0x1 #define PS1 0x2 #define PS2 0x4 /* * Bit Definitions * */ #define _DEPRECATED __attribute__((__deprecated__)) #ifndef BANKMASK #define BANKMASK(addr) ((addr)&01Fh) #endif extern volatile __bit CAL0 @ (((unsigned) &OSCCAL)*8) + 1; #define CAL0_bit BANKMASK(OSCCAL), 1 extern volatile __bit CAL1 @ (((unsigned) &OSCCAL)*8) + 2; #define CAL1_bit BANKMASK(OSCCAL), 2 extern volatile __bit CAL2 @ (((unsigned) &OSCCAL)*8) + 3; #define CAL2_bit BANKMASK(OSCCAL), 3 extern volatile __bit CAL3 @ (((unsigned) &OSCCAL)*8) + 4; #define CAL3_bit BANKMASK(OSCCAL), 4 extern volatile __bit CAL4 @ (((unsigned) &OSCCAL)*8) + 5; #define CAL4_bit BANKMASK(OSCCAL), 5 extern volatile __bit CAL5 @ (((unsigned) &OSCCAL)*8) + 6; #define CAL5_bit BANKMASK(OSCCAL), 6 extern volatile __bit CAL6 @ (((unsigned) &OSCCAL)*8) + 7; #define CAL6_bit BANKMASK(OSCCAL), 7 extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0; #define CARRY_bit BANKMASK(STATUS), 0 extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1; #define DC_bit BANKMASK(STATUS), 1 extern volatile __bit FOSC4 @ (((unsigned) &OSCCAL)*8) + 0; #define FOSC4_bit BANKMASK(OSCCAL), 0 extern volatile __bit GP0 @ (((unsigned) &GPIO)*8) + 0; #define GP0_bit BANKMASK(GPIO), 0 extern volatile __bit GP1 @ (((unsigned) &GPIO)*8) + 1; #define GP1_bit BANKMASK(GPIO), 1 extern volatile __bit GP2 @ (((unsigned) &GPIO)*8) + 2; #define GP2_bit BANKMASK(GPIO), 2 extern volatile __bit GP3 @ (((unsigned) &GPIO)*8) + 3; #define GP3_bit BANKMASK(GPIO), 3 extern volatile __bit GPWUF @ (((unsigned) &STATUS)*8) + 7; #define GPWUF_bit BANKMASK(STATUS), 7 extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2; #define ZERO_bit BANKMASK(STATUS), 2 extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3; #define nPD_bit BANKMASK(STATUS), 3 extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4; #define nTO_bit BANKMASK(STATUS), 4 #endif // _PIC10F202_H_ |
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| 你是不是寄存器名稱沒寫對，去編譯器的.H文件里面看看寄存器名稱怎么定義的 |
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PIC10F202 SOT23-6 我是想用GP1做輸入 發(fā)現(xiàn)內部上拉不起作用 用外部上拉程序可以正常工作 GP3的內部上拉就正常 覺得是比較器沒關閉 就發(fā)現(xiàn)寫CMCON0 會下劃紅線 用的X IDE 好像是V2.35吧 |
| 什么芯片？ |
組圖打開中，請稍候......
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