- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- ENTITY mux41 IS
-
- PORT
- (
- a,b,c,d : IN STD_LOGIC;
- s0,s1 : IN STD_LOGIC;
-
- y : OUT STD_LOGIC
- );
- END ;
- ARCHITECTURE a OF mux41 IS
- SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0);
-
- BEGIN
- S<=s1&s0;
- process (s1,s0)
- begin
- case (S)is
- when "00" =>y<=a;
- when "01" =>y<=b;
- when "10" =>y<=c;
- when "11" =>y<=d;
- end case;
- end process;
- END a;
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