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stm32f051無(wú)刷電機(jī)的無(wú)傳感器控制源碼與原理圖及說(shuō)明資料下載

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基于stm32f051的無(wú)刷電機(jī)無(wú)傳感器的控制。成本低，st原代碼

電路原理圖如下：


stm32單片機(jī)源程序如下:


  3. #include "stm32f0xx.h"
  4. #include "definitions.h"
  5. #include "motorcontrolsettings.h"


  8. unsigned char zcfound;
  9. unsigned char phase;
  10. unsigned char autostep;
  11. unsigned char risingdelay;
  12. unsigned char fallingdelay;
  13. unsigned char risingedge;
  14. unsigned char startstate;
  15. unsigned char run;
  16. unsigned char ontimesample;

  18. unsigned short commcounter;
  19. unsigned short step;
  20. unsigned short bemfsample;
  21. unsigned short dcbussample;
  22. unsigned short commcounter;
  23. unsigned short demagcounter;
  24. unsigned short zccounter;
  25. unsigned short commthreshold;
  26. unsigned short demagthreshold;
  27. unsigned short runningdc;
  28. unsigned short potvalue;
  29. unsigned short zcthreshold;
  30. unsigned short dutycyclehold;

  32. unsigned long holdcounter;
  33. unsigned long alignmentcounter;
  34. unsigned long rampspeed;
  35. unsigned long bemfchannel;



  39. void commutate(void);
  40. void commutate2(void);
  41. void motorstartinit(void);
  42. void delay( unsigned long time);
  43. void flashled(unsigned char flashes);
  44. void selftest(void);
  45. unsigned short readadc( unsigned char chnl);

  47. int main(void)
  48. {


  51. // clock chain setup
  52. RCC->CFGR = (4<<18); // set PLL X6 for 24MHZ
  53. RCC->CR = 0x00000083 + (1<<24); //turn PLL on
  54. RCC->CFGR = (4<<18) + 2; // select PLL as clock

  56. RCC->AHBENR = b19+b18+b17; // enable GPIOA, B, C input clock

  58. RCC->APB2ENR = b11+b9+b0; // enable tim1 and ADC input clocks

  60. RCC->APB1ENR = b29; // enable DAC input clock




  65. //**********************************************

  67. delay(5000000) ;  //let power supply settle


  70. selftest();








  79. // port A setup
  80. //GPIOA->MODER = 0x2A2AFFF0; // a5,a4,3,2,6,7 anlg, a8,9,10,12 AF
  81. GPIOA->MODER = 0x2A6AFFF0; // 11 pp, a5,a4,3,2,6,7 anlg, a8,9,10,12 AF
  82. GPIOA->AFRH  = 0x00020222; // pa8,9,10,12 AF2 for timer

  84. // port B setup
  85. // b22 PB11 as output
  86. GPIOB->MODER = 0xA800000F+b22; // b1,0 anlg, b15,14,13 AF
  87. GPIOB->AFRH = 0x22220000;  // b15,14,13,12 AF2 for timer

  89. // port C setup
  90. GPIOC->ODR = 0;
  91.   

  93. // ADC setup
  94. ADC1->CR= b31 ; // start ADC calibration
  95. while( ADC1->CR & b31);  // wait for calibration to complete
  96. while( ADC1->CR & b31);  // wait for calibration to complete
  97. ADC1->CR = 1; // enable ADC
  98. ADC1->CFGR1 = b16; // enable discontinuous mode
  99. ADC1->SMPR = 1;




  104. // comparator setup
  105. // (b25+b24) send comp2 output to tim1 OCref clear
  106. // b27 invert comp2 output
  107. // b16 enable comp2
  108. // b22+b20 select PA5 as inverting input for comp2

  110. // b0 enable comp1
  111. // (b6+b5) select PA0 comp1 inverting input
  112. // b8 send comp1 output to tim1 break
  113. // b11 to invert comp1 output

  115. COMP->CSR = 0;
  116. #ifdef currentlimitenable
  117. COMP->CSR = COMP->CSR + b27+b16+b22+b20+b25+b24;  // cy-by-cy active
  118. #endif
  119. #ifdef overcurrentenable
  120. COMP->CSR = COMP->CSR + b0+b6+b5+b11+b8; //  brk active
  121. #endif


  124. // tim1 setup
  125. TIM1->SMCR = b15+b4+b5+b6; // make ETR input active low
  126. TIM1->CR2= 0;
  127. TIM1->CCR1= 200;
  128. TIM1->CCR2= 200;
  129. TIM1->CCR3= 200;
  130. TIM1->CCR4= 1100;
  131. TIM1->ARR=1200;
  132. TIM1->CR1=0x0001;


  135. // note: b15 b7 and b7 are to enable ETR  based current limit
  136. TIM1->CCMR1= 0x6868 +b15 + b7;
  137. TIM1->CCMR2= 0x6868 +b7;
  138. // b4 for cc4 and b7 for brk interrupt
  139. //TIM1->DIER = b4+b7;  // enable cc4 interrupt
  140. TIM1->DIER = b4+b6;

  142. // DAC setup
  143. DAC->CR = 1; // enable DAC









  153. // set up interrupts
  154. NVIC_EnableIRQ(14);
  155. __enable_irq();

  157. // initialization
  158. run=0;
  159. motorstartinit();

  161. clearmark;






  168. while(1)
  169. { // backgroung loop

  171. if( (TIM1->BDTR & b15)==0) // overcurrent fault condition
  172. {
  173. run=0;
  174. while(1)
  175. {
  176. ledon;
  177. delay(1000000);
  178. ledoff;
  179. delay(1000000);
  180. if( (4095-potvalue)<100)
  181. {
  182. TIM1->BDTR= b15+b11+b10+b12+b13;  //  set MOE
  183. break;
  184. }


  187. } //end of LED flash loop


  190. } // end of if overcurrent




  195. //TIM1->BDTR= b15+b11+b10+b12+b13;  //  set MOE



  199. if( (4095-potvalue)>200) run=255;
  200. if( (4095-potvalue)<100) run=0;

  202. if(run) ledon;
  203. if(run==0) ledoff;



  207. runningdc = ((4095-potvalue)*1200)>>12;
  208. if(runningdc>1195) runningdc=1300;
  209. if(dutycyclehold && (runningdc>600)) runningdc=600;

  211. #ifdef ontimesampleenable
  212. if(runningdc>800) ontimesample=255;
  213. else ontimesample=0;
  214. #endif







  222. //if(COMP->CSR & b30) // comp2
  223. if(COMP->CSR & b14)  // comp1
  224. {
  225. setmark;
  226. }
  227. else
  228. {
  229. //clearmark;
  230. }





  236. //DAC->DHR12R1 = potvalue; // put out for diagnostic purposes




  241. } // end of backgroung loop





  247. }  // end of main









  257. void commutate(void)
  258. {

  260. switch(phase)
  261. {
  262. case 0: // phase AB
  263. TIM1->CCER = b3+b0  +b7+b4 +b8; //
  264. TIM1->CCMR1= 0x4868 +b15 + b7; // force B active low
  265. TIM1->CCMR2= 0x6868 +b7;
  266. break;
  267. case 1: // phase AC
  268. TIM1->CCER = b3+b0  +b4  +b8+b11; //
  269. TIM1->CCMR1= 0x6868 +b15 + b7;
  270. TIM1->CCMR2= 0x6848 +b7; // force C active low
  271. break;
  272. case 2: // phase BC
  273. TIM1->CCER = b4+b7  +b8+b11  +b0;
  274. TIM1->CCMR1= 0x6868 +b15 + b7;
  275. TIM1->CCMR2= 0x6848 +b7; // force C active low
  276. break;
  277. case 3: // phase BA
  278. TIM1->CCER = b4+b7 +b3+b0 +b8;
  279. TIM1->CCMR1= 0x6848 +b15 + b7; // force A active low
  280. TIM1->CCMR2= 0x6868 +b7;
  281. break;
  282. case 4: // phase CA
  283. TIM1->CCER = b8+b11 +b3+b0 +b4;
  284. TIM1->CCMR1= 0x6848 +b15 + b7; // force A active low
  285. TIM1->CCMR2= 0x6868 +b7;
  286. break;
  287. case 5: // phase CB
  288. TIM1->CCER = b8+b11 +b4+b7 +b0;
  289. TIM1->CCMR1= 0x4868 +b15 + b7; // force B active low
  290. TIM1->CCMR2= 0x6868 +b7;
  291. break;
  292. } // end of phase switch statement
  293. } // end of commutate function

  295. void commutate2(void)
  296. {

  298. //TIM1->CCER=b10+b8+b6+b4+b2+b0; // enable all 6
  299. switch(phase)
  300. {
  301. case 0: // phase AB
  302. // enable all 6 except AN
  303. // invert AN
  304. TIM1->CCER=b10+b8+b6+b4+b0  +b3;
  305. TIM1->CCMR1=0x4868+b15+b7; // B low, A PWM
  306. TIM1->CCMR2= 0x6858 +b7; // force C ref high (phc en low)
  307. break;
  308. case 1: // phase AC
  309. // enable all 6 except AN
  310. // invert AN
  311. TIM1->CCER=b10+b8+b6+b4+b0  +b3;
  312. TIM1->CCMR1=0x5868+b15+b7; // force B high and A PWM
  313. TIM1->CCMR2= 0x6848 +b7; // force C ref low
  314. break;
  315. case 2: // phase BC
  316. // enable all 6 except BN
  317. // invert BN
  318. TIM1->CCER=b10+b8+b4+b2+b0 +b7;
  319. TIM1->CCMR1=0x6858+b15+b7; // force B PWM and A high
  320. TIM1->CCMR2= 0x6848 +b7; // force C ref low
  321. break;
  322. case 3: // phase BA
  323. // enable all 6 except BN
  324. // invert BN
  325. TIM1->CCER=b10+b8+b4+b2+b0 +b7;
  326. TIM1->CCMR1=0x6848+b15+b7; // force B PWM and A ref low
  327. TIM1->CCMR2= 0x6858 +b7; // force C ref high
  328. break;
  329. case 4: // phase CA
  330. // enable all 6 except CN
  331. // invert CN
  332. TIM1->CCER=b8+b6+b4+b2+b0 +b11; // enable all 6 except CN
  333. TIM1->CCMR1=0x5848+b15+b7; // force B high and A ref low
  334. TIM1->CCMR2= 0x6868 +b7; // force C PWM
  335. break;
  336. case 5: // phase CB
  337. // enable all 6 except CN
  338. // invert CN
  339. TIM1->CCER=b8+b6+b4+b2+b0 +b11; // enable all 6 except CN
  340. TIM1->CCMR1=0x4858+b15+b7; // force B low and A high
  341. TIM1->CCMR2= 0x6868 +b7; // force C PWM
  342. break;
  343. } // end of phase switch statement
  344. } // end of commutate2 function


  347. // pwmisr runs just at the end of each PWM cycle
  348. void pwmisr(void)
  349. {

  351. //**********************************************************

  353. unsigned long long0;

  355. ADC1->CHSELR = bemfchannel; // set ADC MUX to proper bemf channel
  356. ADC1->CR = b2;  // start adc conversion
  357. // housekeeping increment of some timers while adc is converting
  358. zccounter++;  // housekeeping increment of some timers while adc is converting
  359. alignmentcounter++;
  360. holdcounter++;
  361. while((ADC1->CR & b2)==b2) ; // wait for conversion to complete
  362. bemfsample= ADC1->DR;

  364. //DAC->DHR12R1 = bemfsample; // put out for diagnostic purposes



  368. // autostep is true during ramping up
  369. if(autostep)
  370. {
  371. commcounter++;
  372.   if(commcounter>step)
  373.   {
  374.   commcounter=0;
  375.   phase++;
  376.   if(phase>5) phase=0;
  377.   commutate2();

  379.   }
  380. } // end of if(autostep)


  383. if(run==0) startstate=0;

  385. switch(startstate)
  386. {
  387. case 0:
  388. TIM1->CCER = 0;
  389. if(run)
  390. {
  391. motorstartinit();
  392. startstate=5;
  393. }
  394. break;

  396. case 5: // setup alignment
  397. TIM1->CCR1= alignmentdc;
  398. TIM1->CCR2= alignmentdc;
  399. TIM1->CCR3= alignmentdc;
  400. phase=0;
  401. commutate2();
  402. alignmentcounter=0;
  403. startstate=10;
  404. break;

  406. case 10: // timing out alignment
  407.   if(alignmentcounter>alignmenttime)
  408.   {
  409.   rampspeed=1;
  410.   commcounter=0;
  411.   autostep=255;
  412.   TIM1->CCR1= rampupdc;
  413.   TIM1->CCR2= rampupdc;
  414.   TIM1->CCR3= rampupdc;
  415.   startstate=20;
  416.   }
  417. break;

  419. case 20: // ramping up
  420. rampspeed = rampspeed+rampuprate; // accelerate
  421. long0 = 4000000000;
  422. long0 = long0/rampspeed; // step time = constant/speed
  423. if(long0>30000) long0=30000;
  424. step=long0;
  425.   if(step<=minstep)
  426.   {
  427.   holdcounter=0;
  428.   startstate=100;
  429.   }
  430. break;

  432. case 100: // wait for hold time, holding at speed to allow sync
  433. if(holdcounter>holdtime) startstate=110;
  434. break;

  436. case 110: // wait to get into phase 5
  437. if(phase==5) startstate=120;
  438. break;

  440. case 120: // wait for leading edge of phase 0 (commutation)
  441. if(phase==0)
  442. {
  443. demagcounter=0;
  444. demagthreshold = (step*demagallowance)>>8;
  445. startstate=130;
  446. }
  447. break;

  449. case 130: // wait out demag time (for current in phase to go to 0)
  450. demagcounter++;
  451.   if(demagcounter>demagthreshold)
  452.   {
  453.   startstate=140;
  454.   }
  455. break;

  457. case 140: // looking for zero crossing of bemf
  458. if( zcfound && (zccounter>maxstep) )
  459. {
  460. startstate=0;
  461. break;
  462. }


  465. if(risingedge)
  466. {
  467.   if((bemfsample>zcthreshold)||(zccounter>maxstep) )
  468.   {
  469.   if(zcfound) step = zccounter;
  470.   commthreshold = (step*risingdelay)>>8;
  471.   zccounter=0;
  472.   commcounter=0;
  473.   startstate=150;
  474.   risingedge=0;
  475.   zcfound=255;
  476.   autostep=0;
  477.   }
  478. }
  479. else
  480. {
  481.   if((bemfsample<zcthreshold)||(zccounter>maxstep) )
  482.   {
  483.   if(zcfound) step = zccounter;
  484.   commthreshold = (step*fallingdelay)>>8;
  485.   zccounter=0;
  486.   commcounter=0;
  487.   startstate=150;
  488.   risingedge = 255;
  489.   zcfound=255;
  490.   autostep=0;
  491.   }
  492. }
  493. break;

  495. case 150:  // wait out commutation delay (nominal 1/2 step time)
  496. TIM1->CCR1= runningdc;
  497. TIM1->CCR2= runningdc;
  498. TIM1->CCR3= runningdc;
  499. commcounter++;
  500.   if(commcounter>commthreshold)
  501.   {
  502.   phase++; // commutate
  503.   if(phase>5) phase=0;
  504. commutate2();
  505.   demagcounter=0;
  506.   demagthreshold = (step*demagallowance)>>8;
  507.   startstate=130;  // go back to wait out demag
  508.   if(dutycyclehold) dutycyclehold--;
  509.   }
  510. break;
  511. } // end of startstate state machine






  518. ADC1->CHSELR = b2; // set ADC MUX to pot channel (ain2)
  519. ADC1->CR = b2;  // start adc conversion

  521. // switch statement determines next bemf ADC input channel
  522. switch(phase)
  523. {
  524. case 0: // ab
  525. bemfchannel= 1<<8 ; // read phase c
  526. break;
  527. case 1: // ac
  528. bemfchannel= 1<<7 ; // read phase b
  529. break;
  530. case 2:  // bc
  531. bemfchannel= 1<<6 ; // read phase a
  532. break;
  533. case 3:  // ba
  534. bemfchannel= 1<<8 ; // read phase c
  535. break;
  536. case 4:  // ca
  537. bemfchannel= 1<<7 ; // read phase b
  538. break;
  539. case 5:  // cb
  540. bemfchannel= 1<<6 ; // read phase a
  541. break;
  542.   
  543. } // end of phase switch statement


  546. if(ontimesample)
  547. {
  548. GPIOC->MODER = 0x54000000; // C15,14,13 PP to turn on attenuator
  549. TIM1->CCR4 = 100; // move isr to halfway thry on time
  550. //zcthreshold = 620;  // for 12V bus
  551. long0 = dcbussample;
  552. long0 = long0 * 599;
  553. long0 = long0>>10;
  554. zcthreshold = long0;
  555. }
  556. else
  557. {
  558. GPIOC->MODER = 0; // turn attenuator off
  559. TIM1->CCR4 = 1100;
  560. zcthreshold = 200;  // threshold to about zero
  561. }

  563. while((ADC1->CR & b2)==b2) ; // wait for conversion to complete
  564. potvalue=  ADC1->DR;

  566. ADC1->CHSELR = b9; // set ADC MUX to dc bus channel (ain9)
  567. ADC1->CR = b2;  // start adc conversion
  568. while((ADC1->CR & b2)==b2) ; // wait for conversion to complete
  569. dcbussample =  ADC1->DR;

  571. DAC->DHR12R1 = dcbussample; // put out for diagnostic purposes


  574. //**************************************************************

  576. // clear interrupt
  577. TIM1->SR &= ~0x01F;
  578. NVIC_ClearPendingIRQ(14);
  579. }





  585. void  motorstartinit(void)
  586. {
  587. TIM1->CCER = 0;

  589. // b12 to enable brk input
  590. // b13 for break polarity
  591. // (b15+b11);  //  set MOE

  593. TIM1->BDTR= b15+b11+b10+b12+b13;  //  set MOE


  596. // ADC count used as zero crossing threshold
  597. // may need to be set higher/lower for higher/lower bemf motors
  598. // setting too low may cause noise sensitivity issues
  599. zcthreshold = 200 ;


  602. ontimesample=0;
  603. phase = 0;
  604. holdcounter=0;
  605. startstate=0;
  606. commcounter=0;
  607. step=3670; // unit is 50uS pwm periods
  608. autostep = 0;
  609. risingedge = 0;
  610. zcfound=0;
  611. alignmentcounter=0;
  612. rampspeed=1;
  613. commthreshold=0;

  615. // risingdelay and fallingdelay control the time delay waited
  616. // between zero crossing detection and commutation.  The nominal
  617. // value is 128 which means 128/256 or 1/2 of a step time, which
  618. // is the phase shift between line to neutral zero crossing
  619. // (what is actually detected) and line to line zero cross
  620. // (nominal correct commutation time)
  621. // adjustment will advance or delay commutation (phase advance)
  622. risingdelay=128;
  623. fallingdelay=128;

  625. // sets open loop motor voltage (speed) 1200 for 100% duty cycle
  626. runningdc = 600;

  628. dutycyclehold=100;

  630. } // end of motor start init function



  634. void delay( unsigned long time)  // 1000 is 200 usec
  635. {
  636. while(time>0) time--;
  637. }



  641. void selftest(void)
  642. {

  644. unsigned short word0;


  647. // port B setup
  648. GPIOB->ODR = 0;
  649. /*
  650. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  651. pp pp pp pp in pp pp pp pp pp pp pp pp pp an an
  652. 01 01 01 01 00 01 01 01 01 01 01 01 01 01 11 11
  653.   5     5     1     5     5     5     5     F
  654. */
  655. GPIOB->MODER = 0x5515555F;


  658. //test for jumper from P6-2(pb10) to P6-1(pb11)and return from selftest if not
  659. GPIOB->ODR &= ~b10;
  660. delay(1000);
  661. if((GPIOB->IDR & b11) != 0) return;

  663. GPIOB->ODR |= b10;
  664. delay(1000);
  665. if((GPIOB->IDR & b11) != b11) return;

  667. GPIOB->ODR  &= ~b10;
  668. delay(1000);
  669. if((GPIOB->IDR & b11) != 0) return;

  671. GPIOB->ODR  |= b10;
  672. delay(1000);
  673. if((GPIOB->IDR & b11) != b11) return;

  675. // program is in test mode

  677. // port A setup
  678. GPIOA->ODR = 0;
  679. /*
  680. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  681. in af af in pp pp pp pp an an an an an an an an
  682. 00 10 10 00 01 01 01 01 11 11 11 11 11 11 11 11
  683.   2     8     5     5     F     F     F     F
  684. */
  685. GPIOA->MODER = 0x2855FFFF;


  688. // comparator setup
  689. COMP->CSR = 0;
  690. #ifdef currentlimitenable
  691. COMP->CSR = COMP->CSR + b27+b16+b22+b20+b25+b24;  // cy-by-cy active
  692. #endif
  693. #ifdef overcurrentenable
  694. COMP->CSR = COMP->CSR + b0+b6+b5+b11+b8; //  brk active
  695. #endif

  697. // ADC setup
  698. ADC1->CR= b31 ; // start ADC calibration
  699. while( ADC1->CR & b31);  // wait for calibration to complete
  700. while( ADC1->CR & b31);  // wait for calibration to complete
  701. ADC1->CR = 1; // enable ADC
  702. ADC1->CFGR1 = b16; // enable discontinuous mode
  703. ADC1->SMPR = 1;


  706. // routine to manually test pot and LED
  707. while(1)
  708. {

  710. potvalue = 4095 - readadc(2);

  712. switch((potvalue>>9))
  713. {
  714. case 0:
  715. ledoff;
  716. break;
  717. case 1:
  718. ledon;
  719. break;
  720. case 2:
  721. ledoff;
  722. break;
  723. case 3:
  724. ledon;
  725. break;
  726. case 4:
  727. ledoff;
  728. break;
  729. case 5:
  730. ledon;
  731. break;
  732. case 6:
  733. ledoff;
  734. break;
  735. case 7:
  736. ledon;
  737. break;
  738. case 8:
  739. break;
  740. }  // end of pot test case statement

  742. //test for jumper from P6-2(pb10) to P6-1(pb11)and break out of loop if not
  743. GPIOB->ODR &= ~b10;
  744. delay(1000);
  745. if((GPIOB->IDR & b11) != 0) break;

  747. GPIOB->ODR |= b10;
  748. delay(1000);
  749. if((GPIOB->IDR & b11) != b11) break;

  751. GPIOB->ODR  &= ~b10;
  752. delay(1000);
  753. if((GPIOB->IDR & b11) != 0) break;

  755. GPIOB->ODR  |= b10;
  756. delay(1000);
  757. if((GPIOB->IDR & b11) != b11) break;

  759. } // end of pot test endless loop

  761. ledoff;
  762. delay(19999999);

  764. // now test DC bus sensing
  765. word0 = readadc(9); // read bemfa
  766. if(word0<1430) flashled(11);
  767. if(word0>1748) flashled(12);

  769. // now test bridge outputs and bemf sensing
  770. phaseadisable;
  771. phasebdisable;
  772. phasecdisable;

  774. phaseahigh;
  775. phaseblow;
  776. phaseclow;

  778. // enable A and set high.  disable B and C
  779. phaseaenable;
  780. delay(500);  // wait 100 usec for settling

  782. word0 = readadc(6); // read bemfa
  783. if(word0<2048) flashled(13);  // fault if pha not high

  785. word0 = readadc(7); // read bemfb
  786. if(word0<2048) flashled(14);  // fault if phb not high

  788. word0 = readadc(8); // read bemfc
  789. if(word0<2048) flashled(15);  // fault if phc not high

  791. // now enable B low
  792. phasebenable;
  793. delay(500);  // wait 100 usec for settling
  794. word0 = readadc(7); // read bemfb
  795. phasebdisable;
  796. if(word0>2048) flashled(21);  // fault if phb not low

  798. // now enable C low
  799. phasecenable;
  800. delay(500);  // wait 100 usec for settling
  801. word0 = readadc(8); // read bemfc
  802. phasecdisable;
  803. if(word0>2048) flashled(22);  // fault if phc not low

  805. phaseadisable;
  806. phasebenable;
  807. phasebhigh;

  809. // B is high, A and C disabled
  810. delay(500);  // wait 100 usec for settling
  811. word0 = readadc(6); // read bemfa
  812. if(word0<2048) flashled(23);  // fault if pha not high

  814. // disable verified for all three phases

  816. phaseadisable;
  817. phasebdisable;
  818. phasecdisable;

  820. // activate phase AB
  821. phaseahigh;
  822. phaseblow;
  823. phaseaenable;
  824. phasebenable;
  825. delay(500);  // wait 100 usec for settling
  826. word0 = readadc(6); // read bemfa
  827. if(word0<2048) flashled(24);  // fault if pha not high
  828. word0 = readadc(7); // read bemfb
  829. if(word0>2048) flashled(24);  // fault if phb not low

  831. // activate phase BA
  832. phasebhigh;
  833. phasealow;
  834. delay(500);  // wait 100 usec for settling
  835. word0 = readadc(6); // read bemfa
  836. if(word0>2048) flashled(25);  // fault if pha not low
  837. word0 = readadc(7); // read bemfb
  838. if(word0<2048) flashled(25);  // fault if phb not high

  840. // activate phase AC
  841. phasebdisable;
  842. phaseahigh;
  843. phaseclow;
  844. phasecenable;
  845. delay(500);  // wait 100 usec for settling
  846. word0 = readadc(6); // read bemfa
  847. if(word0<2048) flashled(31);  // fault if pha not high
  848. word0 = readadc(8); // read bemfc
  849. if(word0>2048) flashled(31);  // fault if phc not low

  851. // activate phase CA
  852. phasechigh;
  853. phasealow;
  854. delay(500);  // wait 100 usec for settling
  855. word0 = readadc(6); // read bemfa
  856. if(word0>2048) flashled(32);  // fault if pha not low
  857. word0 = readadc(8); // read bemfc
  858. if(word0<2048) flashled(32);  // fault if phc not high

  860. // activate phase BC
  861. phaseadisable;
  862. phasebenable;
  863. phasebhigh;
  864. phaseclow;
  865. delay(500);  // wait 100 usec for settling
  866. word0 = readadc(7); // read bemfb
  867. if(word0<2048) flashled(33);  // fault if phb not high
  868. word0 = readadc(8); // read bemfc
  869. if(word0>2048) flashled(33);  // fault if phc not low

  871. // activate phase CB
  872. phasechigh;
  873. phaseblow;
  874. delay(500);  // wait 100 usec for settling
  875. word0 = readadc(7); // read bemfb
  876. if(word0>2048) flashled(34);  // fault if phb not low
  877. word0 = readadc(8); // read bemfc
  878. if(word0<2048) flashled(34);  // fault if phc not high

  880. // all 6 phases have been tested (voltage sensing)

  882. phaseadisable;
  883. phasebdisable;
  884. phasecdisable;

  886. // activate phase AB  (should not trip)
  887. phaseahigh;
  888. phaseblow;
  889. phaseaenable;
  890. phasebenable;
  891. delay(500);  // wait 100 usec for settling
  892. if(COMP->CSR & b30) flashled(35); // comp2 at 2.24A threshold

  894. // now turn on C lower (should trip)
  895. phaseclow;
  896. phasecenable;
  897. delay(500);  // wait 100 usec for settling
  898. if((COMP->CSR & b30)==0) flashled(41); // comp2 at 2.24A threshold

  900. // overcurrent (higher threshold) should be low
  901. if((COMP->CSR & b14)) flashled(42); // comp1  high threshold


  904. phaseadisable;
  905. phasebdisable;
  906. phasecdisable;
  907. ledon;

  909. while(1)
  910. {
  911. word0=0;
  912. // break out of loop when jumper restored
  913. GPIOB->ODR &= ~b10;
  914. delay(1000);
  915. if((GPIOB->IDR & b11) != 0) word0=0;
  916. else word0++;
  917. GPIOB->ODR |= b10;
  918. delay(1000);
  919. if((GPIOB->IDR & b11) != b11) word0=0 ;
  920. else word0++;
  921. GPIOB->ODR  &= ~b10;
  922. delay(1000);
  923. if((GPIOB->IDR & b11) != 0) word0=0 ;
  924. ……………………

  926. …………限于本文篇幅 余下代碼請(qǐng)從51黑下載附件…………
復(fù)制代碼

所有資料51hei提供下載:

en.DM00072008.pdf

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en.DM00073153.pdf

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說(shuō)明材料

en.steval-ihm043v1_bom.pdf

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器件清單

en.steval-ihm043v1_fw.zip

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代碼

en.steval-ihm043v1_schematic.pdf

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原理圖
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