module jishuqi_jsp(clk,clrn,jm,jf,js,cout_1s,qm,qf,qs,cout);
input clk,clrn,cout_1s,jm,jf,js;
output[7:0] qm,qf,qs,cout;
reg [7:0] qm,qf,qs,cout;
always @(posedge clk or negedge clrn)
begin
if(~clrn){qm[7:0],qf[7:0],qs[7:0]} = 0;
else if(~cout_1s)
{qm,qf,qs} = {jm,jf,js};
begin
{qm[7:0],qf[7:0],qs[7:0]} = {qm[7:0],qf[7:0],qs[7:0]} + 1;
if ({qm[7:0],qf[7:0],qs[7:0]} ==1) cout =1;
else cout = 0 ;
end
end
endmodule
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