quartues編寫(xiě)的計(jì)數(shù)器 modelsim仿真沒(méi)有輸出

ID:353926 · 發(fā)表于 2020-5-22 15:29

quartues編寫(xiě)的一個(gè)計(jì)數(shù)器，，modelsim仿真時(shí)的輸出波形是直線。。付給初值后一直輸出初值，clk顯示正常
激勵(lì)文件

library ieee;

use ieee.std_logic_1164.all;

entity clock_tb is

end entity clock_tb;

architecture behaviour of clock_tb is

component clock

port(

clk: in std_logic;

clr: in std_logic;

seg: out std_logic_vector(7 downto 0);

dig: buffer std_logic_vector(2 downto 0)

);

end component;

signal clk:std_logic;

signal clr:std_logic;

signal seg:std_logic_vector(7 downto 0):="01000000";

signal dig:std_logic_vector(2 downto 0):="000";

begin

u1: clock

port map(

clk=>clk,

clr=>clr,

seg=>seg,

dig=>dig);

process begin

wait for 10 ns; clk<='1';

wait for 10 ns; clk<='0';

end process;

process begin

wait for 0 ns;

clr <= '0'; --復(fù)位開(kāi)始

wait for 200.1 ns;

clr <= '1'; --復(fù)位完成

wait; --持續(xù)等待

end process;

end architecture behaviour;

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