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程序如下。寫入后讀取結(jié)果為0xff
// CONFIG1L
#pragma config FEXTOSC = HS // External Oscillator Selection (HS (crystal oscillator) above 8 MHz; PFM set to high power)
#pragma config RSTOSC = EXTOSC_4PLL// Reset Oscillator Selection (EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits)
// CONFIG1H
#pragma config CLKOUTEN = OFF // Clock out Enable bit (CLKOUT function is disabled)
#pragma config PR1WAY = ON // PRLOCKED One-Way Set Enable bit (PRLOCK bit can be cleared and set only once)
#pragma config CSWEN = ON // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
#pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)
// CONFIG2L
#pragma config MCLRE = EXTMCLR // MCLR Enable bit (If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR )
#pragma config PWRTS = PWRT_OFF // Power-up timer selection bits (PWRT is disabled)
#pragma config MVECEN =OFF // Multi-vector enable bit (Multi-vector enabled, Vector table used for interrupts)
#pragma config IVT1WAY = ON // IVTLOCK bit One-way set enable bit (IVTLOCK bit can be cleared and set only once)
#pragma config LPBOREN = OFF // Low Power BOR Enable bit (ULPBOR disabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled , SBOREN bit is ignored)
// CONFIG2H
#pragma config BORV = VBOR_2P45 // Brown-out Reset Voltage Selection bits (Brown-out Reset Voltage (VBOR) set to 2.45V)
#pragma config ZCD = OFF // ZCD Disable bit (ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON)
#pragma config PPS1WAY = ON // PPSLOCK bit One-Way Set Enable bit (PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle)
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config DEBUG = OFF // Debugger Enable bit (Background debugger enabled)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Extended Instruction Set and Indexed Addressing Mode disabled)
// CONFIG3L
#pragma config WDTCPS = WDTCPS_31// WDT Period selection bits (Divider ratio 1:65536; software control of WDTPS)
#pragma config WDTE = OFF // WDT operating mode (WDT Disabled; SWDTEN is ignored)
// CONFIG3H
#pragma config WDTCWS = WDTCWS_7// WDT Window Select bits (window always open (100%); software control; keyed access not required)
#pragma config WDTCCS = SC // WDT input clock selector (Software Control)
// CONFIG4L
#pragma config BBSIZE = BBSIZE_512// Boot Block Size selection bits (Boot Block size is 512 words)
#pragma config BBEN = OFF // Boot Block enable bit (Boot block disabled)
#pragma config SAFEN = OFF // Storage Area Flash enable bit (SAF disabled)
#pragma config WRTAPP = OFF // Application Block write protection bit (Application Block not write protected)
// CONFIG4H
#pragma config WRTB = OFF // Configuration Register Write Protection bit (Configuration registers (300000-30000Bh) not write-protected)
#pragma config WRTC = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
#pragma config WRTSAF = OFF // SAF Write protection bit (SAF not Write Protected)
#pragma config LVP = ON // Low Voltage Programming Enable bit (Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored)
// CONFIG5L
#pragma config CP = OFF // PFM and Data EEPROM Code Protection bit (PFM and Data EEPROM code protection disabled)
// CONFIG5H
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
#include <xc.h>
#include <stdbool.h>
#include <stdint.h>
//#define uint8 unsigned char
//#define uint8_t unsigned char
//#define uint16_t unsigned short
void DATAEE_WriteByte(uint16_t bAdd, uint8_t bData);//EEPROM???
uint8_t DATAEE_ReadByte(uint16_t bAdd); //EEPROM???
void DATAEE_WriteByte(uint16_t bAdd, uint8_t bData)
{
uint8_t GIEBitValue = INTCON0bits.GIE;
NVMADRH = (uint8_t)((bAdd >> 8) & 0x03);
NVMADRL = (uint8_t)(bAdd & 0xFF);
NVMDAT = bData;
NVMCON1bits.NVMREG = 0;
NVMCON1bits.WREN = 1;
INTCON0bits.GIE = 0; // Disable interrupts
NVMCON2 = 0x55;
NVMCON2 = 0xAA;
NVMCON1bits.WR = 1;
// Wait for write to complete
while (NVMCON1bits.WR)
{
}
NVMCON1bits.WREN = 0;
INTCON0bits.GIE = GIEBitValue; // restore interrupt enable
}
uint8_t DATAEE_ReadByte(uint16_t bAdd)
{
NVMADRH = (uint8_t)((bAdd >> 8) & 0x03);
NVMADRL = (uint8_t)(bAdd & 0xFF);
NVMCON1bits.NVMREG = 0;
NVMCON1bits.RD = 1;
NOP(); // NOPs may be required for latency at high frequencies
NOP();
return (NVMDAT);
}
void main(void) //???
{
// TRISC3 = 0;//PORTD???
// LATC3=0;
TRISB7 = 0;//PORTD???
LATB7=0;
// unsigned int hh=12000;
uint8_t qq=0x00;
// while(hh--);LATB7=1;
uint16_t dataeeAddr = 0x30;
uint8_t dataeeData = 0x50;
DATAEE_WriteByte(dataeeAddr, dataeeData);
qq = DATAEE_ReadByte(dataeeAddr);
if(qq==0xff)
{ //LATC3=1;
LATB7=1;
}else//if(qq==0x50)
{ // LATC3=0;
LATB7=0;
}
while(1){
}
}
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