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這是將鎖存器的輸入連接到稱(chēng)為 data_in 的輸入線(xiàn)的 AHDL 代碼，
鎖存器的輸出到稱(chēng)為 data_out 的輸出線(xiàn)，以及到輸入的使能線(xiàn)
稱(chēng)為 latch_enable：
下面是指定八位鎖存器的方法：
- Latch
- A latch in AHDL has two inputs – D and En, and one output Q. When En is low, the output
- Q does not change. When En is high, the output Q is equal to the input D. Thus, when En is
- low, it will hold the value which was on the D input when En went from high to low. To use
- a latch in AHDL, declare it in the VARIABLE section of the program:
- VARIABLE
- A : LATCH;
- will define a one-bit latch. To specify what should on the D input of A, use A.d. To specify
- what should on the En input of A, use A.ena. To use the Q output, refer to A.q.
- Here is the way to specify an eight-bit latch:
- VARIABLE
- A[7..0] : LATCH;
- Here is AHDL code to connect the inputs of the latch to input lines called data_in, the
- outputs of the latch to output lines called data_out, and the the enable lines to an input
- called latch_enable:
- SUBDESIGN my_latch
- (
- data_in[7..0] : INPUT;
- latch_enable : INPUT;
- data_out[7..0] : OUTPUT;
- )
- VARIABLE
- A[7..0] : LATCH;
- BEGIN
- A[].d = data_in[];
- A[].ena = latch_enable;
- data_out[] = A[].q;
- END;
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