After the Data Ready (DR) has been set high a valid data packet is available in the RX data register. This
may be clocked out in RX mode or standby mode. After the data has been clocked out through the SPI the
Data Ready (DR) and Address Match (AM) pins are reset to low.
看上面這段話， DR 被置位，有效的數(shù)據(jù)包將在RX數(shù)據(jù)寄存器變?yōu)榭捎玫模?數(shù)據(jù)時鐘輸出在RX模式和待機模式， 顯然一開機DR將被置位
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