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JTAG時(shí)鐘導(dǎo)致的DM648網(wǎng)口異常

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ID:114320 發(fā)表于 2016-4-15 03:29 | 只看該作者 回帖獎(jiǎng)勵(lì) |正序?yàn)g覽 |閱讀模式
    今天看到了個(gè)帖子,關(guān)于DM648網(wǎng)口異常的。最終原因是JTAG的TCLK沒有下拉導(dǎo)致。下面是原帖部分內(nèi)容:
     We've been having problems with Ethernet comms on our custom board……
     The root of the problem is the need for a pull down on the TCK pin, as per TI Advisory note 1.1.4. I added this and the port started to behave itself instantly.      

    在網(wǎng)上搜到相關(guān)的注釋及說明:
    因?yàn)镴TAG的TCLK與網(wǎng)絡(luò)部分的STCICLK共用,STCICLK需要默認(rèn)下拉,而該引腳在DSP內(nèi)部默認(rèn)上拉,所以會(huì)導(dǎo)致網(wǎng)絡(luò)模塊異常。
    Figure Workaround Example
    Advisory 1.1.4
    Revision(s) Affected Details
    3-Port Ethernet Switch Subsystem (3PSW) clocking problem normal functional operation earlier (JTAG controller clock) internally shared 3-Port Ethernet Switch Subsystem's (3PSW) STCICLK test debug mode. order 3-Port Ethernet Switch Subsystem (3PSW) proper clocking normal functional operation, STCICLK needs held low. since there internal pullup TCK, keeps 3-Port Ethernet Switch Subsystem from locking external REFCLKP/N proper operation. should externally pulled down with resistor.




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