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發(fā)布時(shí)間: 2018-5-17 19:12
正文摘要:2位10進(jìn)制程序 module wcl(q,a,cout,en,clk,clr,sel); input en,clk,clr,sel; output reg [3:0] q; output reg [3:0] a; output reg cout; always @(posedge clk or posedge clr) begin   ... |
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