EDA半加器與全加器vhdl編寫

ID:422604 · 發(fā)表于 2019-11-18 11:14

半加器
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY hadd IS

PORT
(
a,b : IN STD_LOGIC;
s,c : OUT STD_LOGIC
);
END hadd;
ARCHITECTURE one OF hadd IS

BEGIN
s<=a xor b;
c<=a and b;
END one;

全加器
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY f_adder IS

PORT
(
ain,bin,cin : IN STD_LOGIC;

cout,sum : OUT STD_LOGIC
);
END f_adder;
ARCHITECTURE one OF f_adder IS
component hadd
port(a,b :in std_logic;
s,c :out std_logic);
end component;
signal x,y,z : std_logic;
BEGIN
U1:hadd port map(a=>ain,b=>bin,c=>x,s=>y);
U2:hadd port map(a=>y,b=>cin,s=>sum,c=>z);
cout <= (x or z);
END one;

帳號		自動登錄	找回密碼
密碼			立即注冊