ISP1032數(shù)字邏輯EDA設(shè)計(jì)—電子鐘（VHDL代碼）

ID:785709 · 發(fā)表于 2020-6-24 18:39

1、設(shè)計(jì)并用 ISP1032 實(shí)現(xiàn)一個(gè)電子鐘。電子鐘具有下述功能：

a) 試驗(yàn)臺(tái)上的 6 個(gè)數(shù)碼管顯示時(shí)、分、秒。

b) 能使電子鐘復(fù)位（清零）。

c) 能啟動(dòng)或者停止電子鐘運(yùn)行。

d) 再電子鐘停止運(yùn)行狀態(tài)下，能夠修改時(shí)、分、秒的值。

e) 具有報(bào)時(shí)功能，整點(diǎn)時(shí)喇叭鳴叫。

2、要求整個(gè)設(shè)計(jì)分為若干模塊。頂層模塊用原理圖設(shè)計(jì)，底層模塊用 VHDL 語(yǔ)言設(shè)計(jì)。

3、在試驗(yàn)箱上調(diào)試設(shè)計(jì)。

模塊Ⅰ：頂層模塊 clock
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
------------------------------時(shí)鐘主體部分---------------------------
ENTITY clock is
port(clk,clr,adj,clk1 : in std_logic;    -----------clk 為 5KHZ 的時(shí)鐘信號(hào)，clr 為清零信號(hào)，adj 為置數(shù)脈沖，clk1 為以 50KHZ 時(shí)鐘信號(hào)控制響鈴
choice : in std_logic;    ---------用來(lái)選擇時(shí)鐘狀態(tài)的脈沖信號(hào)
lighthour : out std_logic_vector(10 downto 0);
lightmin : out std_logic_vector(7 downto 0);
lightsec : out std_logic_vector(7 downto 0);    -------對(duì)小時(shí)，分鐘和秒的輸出信號(hào)
ring : out std_logic);          -------響鈴信號(hào)
attribute LOC : string;
attribute LOC of RING : signal is "p74";
attribute LOC of CHOICE : signal is "p54";
attribute LOC of LIGHTHOUR : signal is "p9 p41 p6 p8 p12 p68 p5 p60 p10 p52 p56";
attribute LOC of LIGHTMIN : signal is "p32 p48 p33 p79 p18 p70 p46 p83";
attribute LOC of LIGHTSEC : signal is "p4 p14 p75 p37 p71 p47 p50 p29";
attribute LOC of CLK : signal is "p20";
attribute LOC of CLK1 : signal is "p82";
attribute LOC of ADJ : signal is "p15";
attribute LOC of CLR : signal is "p39";       --------鎖定管腳
end clock;
---------------------------時(shí)鐘的結(jié)構(gòu)體部分--------------------------
ARCHITECTURE behavioral of clock is
component counter_60
port(clock : in std_logic;
clk_1s : in std_logic;
adjust : in std_logic;
clr : in std_logic;
load : in std_logic;
s1 : out std_logic_vector(3 downto 0);
s10 : out std_logic_vector(3 downto 0);
co : out std_logic);
end component;                   -------對(duì)模 60 計(jì)數(shù)器的例化
component counter_24
port(clock : in std_logic;
clk_1s : in std_logic;
adjust : in std_logic;
clr : in std_logic;
load : in std_logic;
s1 : out std_logic_vector(3 downto 0);
s10 : out std_logic_vector(6 downto 0));
end component;                   ---------對(duì)模 24 計(jì)數(shù)器的例化
signal sec,a:std_logic;          ---------通過(guò) 2 分頻產(chǎn)生一周期 1s 的 sec 信號(hào)
signal l1,l2,l3:std_logic;       ---------通過(guò) l1，l2，l3 來(lái)判定對(duì)時(shí)，分，秒的修改
signal c1,c2:std_logic;          ---------低位向高位的進(jìn)位信號(hào)，c1 為從秒向分的進(jìn)位，c2 為從分向時(shí)的進(jìn)位
signal load:std_logic_vector(1 downto 0);
signal temp:integer range 0 to 2499;
signal temp1:integer range 0 to 95;          --------計(jì)數(shù)信號(hào)
signal sec_temp:std_logic_vector(7 downto 0); -----對(duì)秒的暫存信號(hào)
------------------------------基本時(shí)鐘進(jìn)程---------------------------
begin
u1 : counter_60 port map (sec,sec,adj,clr,l1,sec_temp(3 downto 0),sec_temp(7 downto 4),c1);
u2 : counter_60 port map (c1,sec,adj,clr,l2,lightmin(3 downto 0),lightmin(7 downto 4),c2);
u3 : counter_24 port map (c2,sec,adj,clr,l3,lighthour(3 downto 0),lighthour(10 downto 4));
lightsec(7 downto 0)<=sec_temp(7 downto 0);    -----3 句例化語(yǔ)句構(gòu)成了基本的時(shí)鐘系統(tǒng)
--------------------------時(shí)鐘的狀態(tài)轉(zhuǎn)換進(jìn)程-----------------------
process (choice)
begin
if (choice'event and choice='1') then
case load is
when "00" => l1<='0';             ---------時(shí)鐘的正常運(yùn)行狀態(tài)
l2<='0';
l3<='0';
load<="01";
when "01" => l1<='0'; -----此狀態(tài)下對(duì)小時(shí)進(jìn)行修改，即 l3=‘1’
l2<='0';
l3<='1';
load<="10";
when "10" => l1<='0';    -----此狀態(tài)下對(duì)分鐘進(jìn)行修改，即 l2=‘1’
l2<='1';
l3<='0';
load<="11";
when others => l1<='1'; -----此狀態(tài)下對(duì) 秒進(jìn)行修改，即 l1=‘1’
l2<='0';
l3<='0';
load<="00";
end case;
end if;
end process;
----------------------------1s 計(jì)數(shù)進(jìn)程------------------------------
process(clk)
begin
if (clk'event and clk='1') then
if (temp=2499) then
temp <= 0;
sec<=not sec;
else
temp <= temp+1;
end if;
end if;
end process;                      --------基本 1s 二分頻計(jì)數(shù)器
-------------------------------響鈴進(jìn)程------------------------------
process(clk1)
begin
if(clk1'event and clk1='1') then
if (temp1=95) then
temp1<=0;
a<=not a;
else
temp1<=temp1+1;
end if;
end if;
end process;
ring<=a when (c2='1' and sec_temp<10 and sec='1') else
'0';
end behavioral;
               ---------通過(guò) sec 的控制產(chǎn)生間斷的整點(diǎn)響鈴，鈴聲為高音 1
模塊Ⅱ：模塊 counter_60
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------計(jì)數(shù)器主體部分----------------------------
entity counter_60 is
port (clock : in std_logic; ------計(jì)數(shù)信號(hào)，即低位的進(jìn)位信號(hào)或時(shí)鐘脈沖信號(hào)
clk_1s : in std_logic;                -------周期 1s 的時(shí)鐘信號(hào)
adjust : in std_logic;                -------調(diào)表置數(shù)信號(hào)
clr : in std_logic;                   --------清零信號(hào)
load : in std_logic;             -----------判定信號(hào)，判定當(dāng)前計(jì)數(shù)器是否處于被修改狀態(tài)
s1 : out std_logic_vector(3 downto 0);    -------計(jì)數(shù)器的個(gè)位輸出（4 位）
s10 : out std_logic_vector(3 downto 0); --------計(jì)數(shù)器的十位輸出（4 位）
co : out std_logic                   --------本位向高位進(jìn)位信號(hào)
);
end counter_60;
------------------------------------計(jì)數(shù)器的結(jié)構(gòu)體部分----------------------------------------
architecture behavioral of counter_60 is
signal s1_temp: std_logic_vector(3 downto 0); ------計(jì)數(shù)器的個(gè)位暫存信號(hào)
signal s10_temp : std_logic_vector(3 downto 0);  ------計(jì)數(shù)器的十位暫存信號(hào)
signal clk,co_temp : std_logic;             -------脈沖控制信號(hào)
begin
clk<=clock when load='0' else
adjust;
            ---------通過(guò)脈沖控制信號(hào)來(lái)控制當(dāng)前正常運(yùn)行或調(diào)表置數(shù)
--------------------------------------模 60 計(jì)數(shù)進(jìn)程--------------------------------------------
process (clk,clr)
begin
if (clr='1') then
s1_temp <= "0000";
s10_temp <= "0000";
elsif (clk'event and clk='1')then
if (s1_temp=9) then
s1_temp <= "0000";
if (s10_temp=5) then
s10_temp <= "0000";
co_temp<='1';
else
co_temp<='0';
s10_temp <= s10_temp+1;
end if;
else
co_temp<='0';
s1_temp <= s1_temp+1;
end if;
end if;
end process;
-----------------------------輸出及顯示------------------------------
s1 <= s1_temp when (clk_1s='1'or load='0') else
"1111";
s10 <= s10_temp when (clk_1s='1' or load='0') else
"1111";
------通過(guò) 1s 時(shí)鐘信號(hào)來(lái)控制在調(diào)表狀態(tài)下對(duì)應(yīng)的輸出燈管進(jìn)行閃爍
co <= co_temp when (load='0') else
'0';
                     ------當(dāng)計(jì)數(shù)器處于被修改狀態(tài)時(shí)不產(chǎn)生進(jìn)位
end behavioral;
模塊Ⅲ：模塊 counter_24
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------計(jì)數(shù)器主體部分---------------------------
entity counter_24 is
port(clock : in std_logic;    -----計(jì)數(shù)信號(hào)，即低位的進(jìn)位信號(hào)
clk_1s : in std_logic;                -------周期 1s 的時(shí)鐘信號(hào)
adjust : in std_logic;             --------調(diào)表置數(shù)信號(hào)
clr : in std_logic;                --------清零信號(hào)
load : in std_logic;  --------判定信號(hào)，判定當(dāng)前計(jì)數(shù)器是否處于被修改狀態(tài)
s1 : out std_logic_vector(3 downto 0);    -------計(jì)數(shù)器的個(gè)位輸出（4 位）
s10 : out std_logic_vector(6 downto 0));
--------計(jì)數(shù)器的十位輸出（由于需 7 段譯碼故用 7 位）
end counter_24;
------------------------------------計(jì)數(shù)器的結(jié)構(gòu)體部分----------------------------------------
architecture behavioral of counter_24 is
signal s1_temp : std_logic_vector(3 downto 0);  -------計(jì)數(shù)器的個(gè)位暫存信號(hào)
signal s10_temp : std_logic_vector(1 downto 0);  ------計(jì)數(shù)器的十位暫存信號(hào)
signal clk : std_logic; --脈沖控制信號(hào)
begin
clk<=clock when load='0' else
adjust;       -------通過(guò)脈沖控制信號(hào)來(lái)控制當(dāng)前正常運(yùn)行或調(diào)表置數(shù)
---------------------------------------模 24 計(jì)數(shù)進(jìn)程-------------------------------------------
process (clk,clr)
begin
if (clr='1') then
s1_temp <= "0000";
s10_temp <= "00";
elsif (clk'event and clk='1') then
if (s1_temp=3 and s10_temp=2) then
s1_temp <= "0000";
s10_temp <= "00";
elsif (s1_temp=9) then
s1_temp<="0000";
s10_temp<=s10_temp+1;
else
s1_temp <= s1_temp+1;
end if;
end if;
end process;
----------------------------------7 段譯碼和輸出顯示進(jìn)程------------------------------------
process(s10_temp)
begin
if (clk_1s='1' or load='0') then
case s10_temp is
when "00" => s10<="1111110";
when "01" => s10<="0110000";
when "10" => s10<="1101101";
when others => null;
end case;
else
s10<="0000000";
end if;
end process;
s1 <= s1_temp when (clk_1s='1' or load='0') else
"1111";
  --------通過(guò) 1s 時(shí)鐘信號(hào)來(lái)控制在調(diào)表狀態(tài)下對(duì)應(yīng)的輸出燈管進(jìn)行閃爍
end behavioral;

以上代碼 word格式:

數(shù)字電子鐘代碼.rar (16.45 KB, 下載次數(shù): 20)

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