FPGA實(shí)現(xiàn)UART收發(fā)數(shù)據(jù) verilog程序

ID:909289 · 發(fā)表于 2021-4-20 20:37

uart用verilog實(shí)現(xiàn)串口調(diào)試助手通信

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:11:32 08/28/08
// Design Name:
// Module Name: my_uart_rx
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module uart_rx(
clk,rst_n,
rs232_rx,rx_data,rx_int,
rx_finish, //cong add
clk_bps,bps_start
);
input clk; // 50MHz主時鐘
input rst_n; //低電平復(fù)位信號
input rs232_rx; // RS232接收數(shù)據(jù)信號
input clk_bps; // clk_bps的高電平為接收或者發(fā)送數(shù)據(jù)位的中間采樣點(diǎn)
output bps_start; //接收到數(shù)據(jù)后，波特率時鐘啟動信號置位
output[7:0] rx_data; //接收數(shù)據(jù)寄存器，保存直至下一個數(shù)據(jù)來到
output rx_int; //接收數(shù)據(jù)中斷信號,接收到數(shù)據(jù)期間始終為高電平
output rx_finish; //cong add
//----------------------------------------------------------------
reg rs232_rx0,rs232_rx1,rs232_rx2,rs232_rx3; //接收數(shù)據(jù)寄存器，濾波用
wire neg_rs232_rx; //表示數(shù)據(jù)線接收到下降沿
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
rs232_rx0 <= 1'b0;
rs232_rx1 <= 1'b0;
rs232_rx2 <= 1'b0;
rs232_rx3 <= 1'b0;
end
else begin
rs232_rx0 <= rs232_rx;
rs232_rx1 <= rs232_rx0;
rs232_rx2 <= rs232_rx1;
rs232_rx3 <= rs232_rx2;
end
end
//下面的下降沿檢測可以濾掉<20ns-40ns的毛刺(包括高脈沖和低脈沖毛刺)，
//這里就是用資源換穩(wěn)定（前提是我們對時間要求不是那么苛刻，因?yàn)檩斎胄盘柎蛄撕脦着模?
//（當(dāng)然我們的有效低脈沖信號肯定是遠(yuǎn)遠(yuǎn)大于40ns的）
assign neg_rs232_rx = rs232_rx3 & rs232_rx2 & ~rs232_rx1 & ~rs232_rx0; //接收到下降沿后neg_rs232_rx置高一個時鐘周期
//----------------------------------------------------------------
reg bps_start_r;
reg[3:0] num; //移位次數(shù)
reg rx_int; //接收數(shù)據(jù)中斷信號,接收到數(shù)據(jù)期間始終為高電平
always @ (posedge clk or negedge rst_n)
if(!rst_n) begin
//cong//bps_start_r <= 1'bz;
bps_start_r <= 1'b0;
rx_int <= 1'b0;
end
else if(neg_rs232_rx) begin //接收到串口接收線rs232_rx的下降沿標(biāo)志信號
bps_start_r <= 1'b1; //啟動串口準(zhǔn)備數(shù)據(jù)接收
rx_int <= 1'b1; //接收數(shù)據(jù)中斷信號使能
end
//cong//else if(num==4'd12) begin //接收完有用數(shù)據(jù)信息
else if(num==4'd10) begin //接收完有用數(shù)據(jù)信息
bps_start_r <= 1'b0; //數(shù)據(jù)接收完畢，釋放波特率啟動信號
rx_int <= 1'b0; //接收數(shù)據(jù)中斷信號關(guān)閉
end
assign bps_start = bps_start_r;
//----------------------------------------------------------------
reg[7:0] rx_data_r; //串口接收數(shù)據(jù)寄存器，保存直至下一個數(shù)據(jù)來到
//----------------------------------------------------------------
reg[7:0] rx_temp_data; //當(dāng)前接收數(shù)據(jù)寄存器
always @ (posedge clk or negedge rst_n)
if(!rst_n) begin
rx_temp_data <= 8'd0;
num <= 4'd0;
rx_data_r <= 8'd0;
end
else if(rx_int) begin //接收數(shù)據(jù)處理
if(clk_bps) begin //讀取并保存數(shù)據(jù),接收數(shù)據(jù)為一個起始位，8bit數(shù)據(jù)，1或2個結(jié)束位
num <= num+1'b1;
case (num)
4'd1: rx_temp_data[0] <= rs232_rx; //鎖存第0bit
4'd2: rx_temp_data[1] <= rs232_rx; //鎖存第1bit
4'd3: rx_temp_data[2] <= rs232_rx; //鎖存第2bit
4'd4: rx_temp_data[3] <= rs232_rx; //鎖存第3bit
4'd5: rx_temp_data[4] <= rs232_rx; //鎖存第4bit
4'd6: rx_temp_data[5] <= rs232_rx; //鎖存第5bit
4'd7: rx_temp_data[6] <= rs232_rx; //鎖存第6bit
4'd8: rx_temp_data[7] <= rs232_rx; //鎖存第7bit
default: ;
endcase
end
//cong//else if(num == 4'd12) begin //我們的標(biāo)準(zhǔn)接收模式下只有1+8+1(2)=11bit的有效數(shù)據(jù)
else if(num == 4'd10) begin //我們的標(biāo)準(zhǔn)接收模式下只有1+8+1(2)=11bit的有效數(shù)據(jù)
num <= 4'd0; //接收到STOP位后結(jié)束,num清零
rx_data_r <= rx_temp_data; //把數(shù)據(jù)鎖存到數(shù)據(jù)寄存器rx_data中
end
end
assign rx_data = rx_data_r;
//assign rx_finish = num==4'd10; //cong add
reg rx_int_1t;
always @ (posedge clk or negedge rst_n)begin
if(!rst_n) begin
rx_int_1t <= 1'b0;
end
else begin
rx_int_1t <= rx_int;
end
end
assign rx_finish = ~rx_int & rx_int_1t;
endmodule

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ID:857680 · 發(fā)表于 2021-5-25 16:59

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