MSP430F5529用DMA接收串口數(shù)據(jù)，并作出回應(yīng)

ID:903336 · 發(fā)表于 2021-9-18 23:03

#include "msp430.h"
#define CPU  ((double)4000000)
#define delay_ms(x) __delay_cycles((long)(CPU*(double)x/1000.0))
#define delay_us(x) __delay_cycles((long)(CPU*(double)x/1000000.0))
#define TX_Num 10       //發(fā)送數(shù)組大小
#define RX_Num 10       //接收數(shù)組大小
#define Frame_Header 0xEE          //接收幀頭
#define Frame_End    0xFF          //接收幀尾
void XT_init(void);                   //晶振初始化函數(shù)
void Receive_Handle(void);             //接收處理函數(shù)
void DMA_init(void);                   //DMA初始化理函數(shù)
unsigned char TxString[TX_Num];       //發(fā)送數(shù)組
unsigned char RxString[RX_Num];       //接收數(shù)組
unsigned char RX_Succeed;             //接收正確標(biāo)志
int main( void )
{
  // Stop watchdog timer to prevent time out reset
  WDTCTL = WDTPW + WDTHOLD;
  XT_init();                               //晶振初始化

  //初始化串口
  P4SEL |= BIT4+BIT5;                      //選擇P4.4、P4.5 為串口1
  UCA1CTL1 |= UCSWRST;                   // **Put state machine in reset**
  UCA1CTL1 |= UCSSEL__ACLK;                //串口時(shí)鐘源為ACLK ，在初始化為32.768kHz
  UCA1BR0 = 3;                            // 32768  9600 (see User's Guide)
  UCA1BR1 = 0;                            // 32768 9600
  UCA1MCTL |= UCBRS_3 + UCBRF_0;          // Modulation UCBRSx=3, UCBRFx=0
  UCA1CTL1 &= ~UCSWRST;                   // **Initialize USCI state machine**
  DMA_init();                            //DMA初始化
  _EINT();
  while(1)
  {
if (RX_Succeed==1)                   //正確接收
{
   RX_Succeed=0;                      //清除接收標(biāo)志
   DMA1CTL|=DMAEN;                      //啟動(dòng)DMA通道1發(fā)送數(shù)據(jù)
}
  }
}

void DMA_init(void)
{
  int i=0;
  DMACTL0 = DMA0TSEL_20|DMA1TSEL_21;          // 通道0接收數(shù)據(jù)，通道1發(fā)送數(shù)據(jù)
  DMA0CTL&=~DMAIFG;                            //先清除通道0中斷標(biāo)志位
  DMA1CTL&=~DMAIFG;                            //先清除通道1中斷標(biāo)志位
  //配置通道0接收
  DMACTL4=DMARMWDIS;                         //禁止任何發(fā)生在CPU 讀寫(xiě)操作時(shí)候的DMA傳輸
  //重復(fù)單次傳輸+開(kāi)啟使能+目標(biāo)地址增加+字節(jié)傳輸 +開(kāi)啟中斷
  DMA0CTL = DMADT_4 + DMAEN + DMADSTINCR_3+DMADSTBYTE+ DMAIE;
  DMA0SZ = RX_Num;                            // 接收字節(jié)大小
  __data16_write_addr((unsigned short) &DMA0SA,(unsigned long) &UCA1RXBUF);//源地址為串口1接收地址
  __data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &RxString);//目的地址是接收數(shù)組

  //配置通道1發(fā)送

  //單次傳輸+源地址增加+字節(jié)傳輸 +電平觸發(fā)+ 開(kāi)啟中斷
  DMA1CTL = DMADT_0 + DMASRCINCR_3  + DMASRCBYTE + DMALEVEL + DMAIE;
  DMA1SZ = TX_Num;                            // 發(fā)送字節(jié)大小
  __data16_write_addr((unsigned short) &DMA1SA,(unsigned long) &TxString);//源地址為發(fā)收數(shù)組
  __data16_write_addr((unsigned short) &DMA1DA,(unsigned long) &UCA1TXBUF);//目的地址是串口1發(fā)送地址

  //初始化發(fā)送數(shù)組
  for(i=0;i<10;i++)
  {
   TxString[i]=0x0a+i;
  }
}

#pragma vector=DMA_VECTOR
__interrupt void DMA_ISR(void)
{
  switch(__even_in_range(DMAIV,4))
  {
  case 0x00:
break;
  case 0x02: //通道0 接收到數(shù)組
Receive_Handle();
break;

  }
}
void Receive_Handle(void)
{
  if(RxString[0]==Frame_Header&&RxString[RX_Num-1]==Frame_End)//數(shù)據(jù)接收正確
  {
//對(duì)數(shù)據(jù)進(jìn)行處理
RX_Succeed=1; //接收正確標(biāo)志
  }

}

void XT_init(void)
{
  P5SEL |= BIT4|BIT5|BIT2|BIT3;                   // Select XT1、XT2
  UCSCTL6 &= ~(XT1OFF|XT2OFF);                   // XT1、XT2 On
  UCSCTL6 |= XCAP_3;                      // Internal load cap
  do
  {
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
SFRIFG1 &= ~OFIFG;                   // Clear fault flags
  }while (SFRIFG1&OFIFG);                // Test oscillator fault flag
  UCSCTL6 &= ~(XT1DRIVE_3+XT2DRIVE0);                // Xtal is now stable, reduce drive strength
  UCSCTL4 =SELA_0+SELS__XT2CLK+SELM__XT2CLK;
  UCSCTL5|=DIVS__4;    //ACLK 32768,SMCLK  1M ，MCLK  4
}

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MSP430F5529用DMA接收串口數(shù)據(jù)，并作出回應(yīng)

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