FPGA幾種特殊分頻方式

1、半整數(shù)分頻占空比不為50%

//說(shuō)明：設(shè)計(jì)的史上最好用的半整數(shù)分頻占空比不為50%，包含設(shè)計(jì)思路

module div_5(clk,clk_div,cnt1,cnt2,temp1,temp2);//N+0.5

input clk;

output clk_div;

output reg[31:0]cnt1,cnt2;

output reg temp1,temp2;

initial begin temp1=0;temp2=1;end   //首先進(jìn)行初始化，temp1=0;temp2=1

parameter N=5;  //設(shè)定分頻系數(shù)為N+0.5

always @(posedge clk)  //temp1上升沿跳變

begin

if(cnt1==2*N)  //2*N

begin cnt1[31:0]<=32'd0;end

else begin cnt1[31:0]<=cnt1[31:0]+32'd1;end

if(cnt1==32'd0) begin temp1<=1;end   //高電平時(shí)間為N+1;

if(cnt1==N+1) begin temp1<=0;end   //低電平時(shí)間為N;

end

always@(negedge clk)  //temp2下降沿跳變

begin

if(cnt2==2*N)  //2*N

begin cnt2[31:0]<=32'd0;end

else begin cnt2[31:0]<=cnt2[31:0]+32'd1;end

if(cnt2==32'd0) begin temp2<=0;end     //低電平時(shí)間為N;

if(cnt2==N) begin temp2<=1;end    //高電平時(shí)間為N+1;

end

assign clk_div=temp1&&temp2;  //邏輯與

endmodule

//如果要進(jìn)行N+0.5分頻

//思路：總的來(lái)說(shuō)要進(jìn)行N+1+N=2N+1次分頻

//在時(shí)鐘的上升沿和下降沿都進(jìn)行跳變

//上升沿進(jìn)行占空比為N+1比N的時(shí)鐘temp1;

//下降沿進(jìn)行占空比為N比N+1的時(shí)鐘temp2;

//最后div=temp1&&temp2 即可得到所需要的半整數(shù)分頻

 

2、奇數(shù)分頻占空比為50%

//說(shuō)明：奇數(shù)分頻。

module div_5(clk,clk_div,cnt1,cnt2,temp1,temp2);//

input clk;

output clk_div;

output reg[31:0]cnt1,cnt2;

output reg temp1,temp2;

parameter N=5;  //設(shè)定分頻系數(shù)

always @(posedge clk)

begin

if(cnt1==N-1)  //N-1進(jìn)行N計(jì)數(shù)

begin cnt1[31:0]<=32'd0;end

else begin cnt1[31:0]<=cnt1[31:0]+32'd1;end

if(cnt1==32'd0) begin temp1<=1;end   //

if(cnt1==(N-1)/2) begin temp1<=0;end   //當(dāng)計(jì)數(shù)到(N-1)/2時(shí)翻轉(zhuǎn)

end

always@(negedge clk)

begin

if(cnt2==N-1)  //N-1

begin cnt2[31:0]<=32'd0;end

else begin cnt2[31:0]<=cnt2[31:0]+32'd1;end

if(cnt2==32'd0) begin temp2<=1;end     //;

if(cnt2==(N-1)/2) begin temp2<=0;end    //當(dāng)計(jì)數(shù)到(N-1)/2時(shí)翻轉(zhuǎn);

end

assign clk_div=temp1||temp2;  //邏輯或

endmodule