數(shù)碼管的動(dòng)態(tài)刷新Verilog源程序

ID:546381 · 發(fā)表于 2019-5-28 17:15

六位八段數(shù)碼管，最后兩位自加首先循環(huán)，同時(shí)在到特定的數(shù)字調(diào)用蜂鳴器“嗶~”

源程序如下:

module Project_Segled2
(
//輸入端口
CLK_50M,CLK_1S,RST_N,
//輸出端口
SEG_DATA,SEG_EN,FM
);
//---------------------------------------------------------------------------
//-- 外部端口聲明
//---------------------------------------------------------------------------
input CLK_50M; //時(shí)鐘的端口,開發(fā)板用的50M晶振
input CLK_1S;
input RST_N; //復(fù)位的端口,低電平復(fù)位
output reg [ 5:0] SEG_EN; //數(shù)碼管使能端口
output reg [ 7:0] SEG_DATA; //數(shù)碼管數(shù)據(jù)端口(查看管腳分配文檔或者原理圖)
output reg FM; //控制蜂鳴器
//---------------------------------------------------------------------------
//-- 內(nèi)部端口聲明
//---------------------------------------------------------------------------
reg [15:0] time_cnt; //用來(lái)控制數(shù)碼管閃爍頻率的定時(shí)計(jì)數(shù)器
reg [15:0] time_cnt_n; //time_cnt的下一個(gè)狀態(tài)
reg [ 2:0] led_cnt; //用來(lái)控制數(shù)碼管亮滅及顯示數(shù)據(jù)的顯示計(jì)數(shù)器
reg [ 2:0] led_cnt_n; //led_cnt的下一個(gè)狀態(tài)
reg [3:0] gewei; // 后兩位的個(gè)位
reg [3:0] shiwei; //后兩位的十位
reg [7:0] GE_DATA; //個(gè)位數(shù)碼管數(shù)據(jù)
reg [7:0] SHI_DATA; //十位數(shù)碼管數(shù)據(jù)
reg [3:0] gewei_n; // 后兩位的個(gè)位
reg beep_reg; //用來(lái)控制蜂鳴器發(fā)聲的寄存器
reg beep_reg_n; //beep_reg的下一個(gè)狀態(tài)
//設(shè)置定時(shí)器的時(shí)間為1ms,計(jì)算方法為 (1*10^3)us / (1/50)us 50MHz為開發(fā)板晶振
parameter SET_TIME_1MS = 16'd50_000;
parameter freq = 16'd47774;
initial
begin
gewei = 4'h5; //初始化個(gè)位十位的值
shiwei=4'h0;
gewei_n=4'h5;
end
//---------------------------------------------------------------------------
//-- 邏輯功能實(shí)現(xiàn)
//---------------------------------------------------------------------------
//時(shí)序電路,用來(lái)給time_cnt寄存器賦值
always @ (posedge CLK_50M or negedge RST_N)
begin
if(!RST_N) //判斷復(fù)位
time_cnt <= 16'h0; //初始化time_cnt值
else
time_cnt <= time_cnt_n; //用來(lái)給time_cnt賦值
end
always @ (posedge CLK_50M)
begin
if(time_cnt == SET_TIME_1MS) //判斷1ms時(shí)間
time_cnt_n = 16'h0; //如果到達(dá)1ms,定時(shí)計(jì)數(shù)器將會(huì)被清零
else
time_cnt_n = time_cnt + 27'h1; //如果未到1ms,定時(shí)計(jì)數(shù)器將會(huì)繼續(xù)累加
end
//時(shí)序電路,用來(lái)給led_cnt寄存器賦值
always @ (posedge CLK_1S or negedge RST_N)
begin
if(!RST_N ) //判斷復(fù)位
begin
gewei = 4'h5; //初始化個(gè)位十位的值
shiwei=4'h0;
end
else if(gewei==4'b1001)
begin
gewei=4'h0;
shiwei=shiwei+1'h1; //如果個(gè)位到十就歸0且讓十位加一
end
else if(shiwei==4'b0100)
begin
shiwei=4'h0; //判斷十位的值如果到4就歸0
end
else
gewei=gewei_n;
end
//組合電路,判斷時(shí)間，實(shí)現(xiàn)控制顯示計(jì)數(shù)器累加
always @ (negedge CLK_1S)
begin
gewei_n = gewei + 1'h1; //如果到達(dá)1s,計(jì)數(shù)器進(jìn)行累加
end
//時(shí)序電路,用來(lái)給gewei寄存器賦值
always @ (posedge CLK_50M or negedge RST_N)
begin
if(!RST_N) //判斷復(fù)位
led_cnt <= 3'h0; //初始化led_cnt值
else
led_cnt <= led_cnt_n; //用來(lái)給led_cnt賦值
end
//組合電路,判斷時(shí)間，實(shí)現(xiàn)控制顯示計(jì)數(shù)器累加
always @ (posedge CLK_50M)
begin
if(time_cnt == SET_TIME_1MS) //判斷1Ms時(shí)間
led_cnt_n = led_cnt + 1'h1; //如果到達(dá)1ms,計(jì)數(shù)器進(jìn)行累加
else
led_cnt_n = led_cnt; //如果未到1ms,計(jì)數(shù)器保持不變
end
//實(shí)現(xiàn)gewei數(shù)據(jù)到數(shù)碼管碼數(shù)的一致
always @ (posedge CLK_50M)
begin
case(gewei)
4'b0000:GE_DATA= 8'b00111111; //0
4'b0001:GE_DATA= 8'b00000110; //1
4'b0010:GE_DATA= 8'b01011011; //2
4'b0011:GE_DATA= 8'b01001111; //3
4'b0100:GE_DATA= 8'b01100110; //4
4'b0101:GE_DATA= 8'b01101101; //5
4'b0110:GE_DATA= 8'b01111101; //6
4'b0111:GE_DATA= 8'b00000111; //7
4'b1000:GE_DATA= 8'b01111111; //8
4'b1001:GE_DATA= 8'b01101111; //9
default:GE_DATA=8'b10111111;
endcase
end
//實(shí)現(xiàn)shiwei數(shù)據(jù)到數(shù)碼管數(shù)的一致
always @ (posedge CLK_50M)
begin
case(shiwei)
4'b0000:SHI_DATA= 8'b00111111; //0
4'b0001:SHI_DATA= 8'b00000110; //1
4'b0010:SHI_DATA= 8'b01011011; //2
4'b0011:SHI_DATA= 8'b01001111; //3
4'b0100:SHI_DATA= 8'b01100110; //4
default:SHI_DATA=8'b10111111;
endcase
end
//組合電路,實(shí)現(xiàn)數(shù)碼管的數(shù)字顯示
always @ (posedge CLK_50M)
begin
case (led_cnt)
3'b000 : SEG_DATA = 8'b00000111; //當(dāng)計(jì)數(shù)器為0時(shí),數(shù)碼管將會(huì)顯示 "7"
3'b001 : SEG_DATA = 8'b00000110; //當(dāng)計(jì)數(shù)器為1時(shí),數(shù)碼管將會(huì)顯示 "1"
3'b010 : SEG_DATA = 8'b01100110; //當(dāng)計(jì)數(shù)器為2時(shí),數(shù)碼管將會(huì)顯示 "4"
3'b011 : SEG_DATA = 8'b00111111; //當(dāng)計(jì)數(shù)器為3時(shí),數(shù)碼管將會(huì)顯示 "0"
3'b100 : SEG_DATA = SHI_DATA; //當(dāng)計(jì)數(shù)器為4時(shí),數(shù)碼管將會(huì)顯示 "十位"
3'b101 : SEG_DATA = GE_DATA; //當(dāng)計(jì)數(shù)器為5時(shí),數(shù)碼管將會(huì)顯示 "個(gè)位"
default: SEG_DATA = 8'b10111111;
endcase
end
always @ (posedge CLK_50M)
begin
case (led_cnt)
3'b000 : SEG_EN = 6'b111110; //當(dāng)計(jì)數(shù)器為0時(shí),數(shù)碼管SEG1顯示
3'b001 : SEG_EN = 6'b111101; //當(dāng)計(jì)數(shù)器為1時(shí),數(shù)碼管SEG2顯示
3'b010 : SEG_EN = 6'b111011; //當(dāng)計(jì)數(shù)器為2時(shí),數(shù)碼管SEG3顯示
3'b011 : SEG_EN = 6'b110111; //當(dāng)計(jì)數(shù)器為3時(shí),數(shù)碼管SEG4顯示
3'b100 : SEG_EN = 6'b101111; //當(dāng)計(jì)數(shù)器為4時(shí),數(shù)碼管SEG5顯示
3'b101 : SEG_EN = 6'b011111; //當(dāng)計(jì)數(shù)器為5時(shí),數(shù)碼管SEG6顯示
default: SEG_EN = 6'b111111;
endcase
end
//控制蜂鳴器
always @ (posedge CLK_50M or negedge RST_N)
begin
if(!RST_N) //判斷復(fù)位
beep_reg <= 1'b0; //初始化beep_reg值
else
beep_reg <= beep_reg_n; //用來(lái)給beep_reg賦值
end
//組合電路,判斷頻率,使蜂鳴器發(fā)聲
always @ (posedge CLK_50M)
begin
if(time_cnt == freq) //判斷分頻值
beep_reg_n = ~beep_reg; //改變蜂鳴器的狀態(tài)
else
beep_reg_n = beep_reg; //蜂鳴器的狀態(tài)保持不變
end
always @ (posedge CLK_50M)
begin
if(gewei==4'h5 && shiwei==4'h0)
FM = beep_reg;
end
endmodule

復(fù)制代碼

所有資料51hei提供下載:

final.zip (3.37 MB, 下載次數(shù): 10)

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數(shù)碼管的動(dòng)態(tài)刷新Verilog源程序

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