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最近做一個(gè)FPGA的小項(xiàng)目，用到NIOS2軟核和DDR2內(nèi)核。昨天編譯DDR2內(nèi)核的時(shí)候遇到一個(gè)錯(cuò)誤：
Error: The DDIO_OUT WYSIWYG primitive "nios_osd_v20:inst|altmemddr:the_altmemddr|altmemddr_controller_phy:altmemddr_controller_phy_inst|altmemddr_phy:altmemddr_phy_inst|altmemddr_phy_alt_mem_phy:altmemddr_phy_alt_mem_phy_inst|altmemddr_phy_alt_mem_phy_clk_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_e4h:auto_generated|ddio_outa[0]" feeding the pin "DDR_CK[0]" has multiple fan-outs
昨晚找了一晚，一直查不出原因。剛剛在國(guó)外的一個(gè)網(wǎng)站上終于找到了答案:)有幾個(gè)人跟我遇到同樣的問(wèn)題，最后原因很簡(jiǎn)單。
“The error was not a bug in Quartus II 7.2 beta, but an error in my own design.... I had not noticed that the sdram_clk and the sdram_clk_n are both bidirectional. When this error is fixed the design compiles. I have not tested the design on my board yet, but hopefully everything works....
Regards
Tom”
開(kāi)始大家都懷疑是版本的問(wèn)題，后來(lái)一位兄弟找到了原因。DDR2內(nèi)核的mem_clk和mem_clk_n都是雙向的，而我在配置的時(shí)候把它們都設(shè)成輸出了。在這里把它共享出來(lái)，希望以后遇到這個(gè)問(wèn)題的朋友可以看到。
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