基于FPGA的信號發(fā)生器程序

ID:440209 · 發(fā)表于 2018-12-5 23:03

基于FPGA的信號發(fā)生器

三角波
//clk:時鐘信號
//reset:復(fù)位信號
//triangle_out:三角波輸出
module triangle(clk,reset,triangle_out);
input clk,reset;
output[7：0] triangle_out;
reg[7:0] triangle_out;
reg[7:0] num; //計數(shù)器
reg reg_1; //加減控制器
always@(posedge clk or posedge rest)
begin
if(reset)
num<=0; //當(dāng)復(fù)位信號為1時輸出為0
else if(reg_1==0)
begin
if(num==8’b11111000)
begin
num<=255;
reg_1<=1; //加至最大值，開始進(jìn)行減法
end
else
num<=num+8; //進(jìn)行加8運算，取出32個點
end
else if(num==8’b00000111)
begin
num<=0;
reg_1<=0; //準(zhǔn)備進(jìn)行加法
end
else
begin
num<=num-8; //進(jìn)行減8運算，需要取出32個點
end
end
always@(num)
begin
triangle_out<=num;//將取出的點輸出，即可實現(xiàn)三角波
end
endmodule
正弦波
//clk:時鐘信號
//reset:復(fù)位信號
//sin_out:正弦波輸出
Module sin(clk,reset,sin_out);
Input clk,reset;
output[7:0]sin_out;
reg[7:0]sin_out;
reg[6:0]num;
always@(posedge clk or posedge reset)
begin
if(reset)
sin_out<=0;
else if(num==63) //共需要64個點
num<=0;
else
num<=num+1;
case(num) //每個點一一對應(yīng)的數(shù)據(jù)
0:sin_out<=255;
1:sin_out<=254;
2:sin_out<=252;
3:sin_out <=249;
4:sin_out <=245;
5:sin_out<= 239;
6:sin_out <= 23;
7:sin_out<= 225;
8:sin_out<=217;
9:sin_ out <=207;
10:sin out<=197;
11:sin out<= 186;
12:sin out <=174;
13:sin_out<=162;
14:sin_out<=150;
15:sin_out<=137;
16:sin_out<=124;
17:sin_out<=112;
18:sin_out<=99;
19:sin_out<=87;
20:sin_out<=75;
21:sin_out<=64;
22:sin_out<=53;
23:sin_out<=43;
24:sin_out<=34;
25:sin_out<=26
26:sin_out<=19;
27:sin_out<=13;
28:sin_out<=8;
29:sin_out<=4;
30:sin_out<=1;
31:sin_out<=0;
32:sin_out<=0;
33:sin_out<=1;
34:sin_out<=4;
35:sin_out<=8;
36:sin_out<=13;
37:sin_out<=19;
38:sin_out<=26;
39:sin_out<=34;
40:sin_out<=43;
41:sin_out<=53;
42:sin_out<=64;
43:sin_out<=75;
44:sin_out<=87;
45:sin_out<=99;
46:sin_out<=112;
47:sin_out<=124;
48:sin_out<=137;
49:sin_out<=150;
50:sin_out<=l62;
51:sin_out<=174;
52:sin_out<=186;
53:sin_out<=197;
54:sin_out<=207;
55:sin_out<=217;
56:sin_out<=225;
57:sin_out<=233;
58:sin_out<=239;
59:sin_out<=245;
60:sin_out<= 249;
61:sin_out <= 252;
62:sin_out <= 254;
63:sin_out <= 255;
default:sin_ out<=8 'bx;
endcase
end
endmodule
//clk:時鐘信號
//reset:復(fù)位信號
//square:方波輸出
module square( clk,reset,square_out) ;
input clk,reset;
output[7:0] square_ out;
reg[7:0] square_out;
reg[5:0] num;
reg reg_2;
always @( posedge clk or posedge reset)
begin
if( reset)
reg_2<=0; //當(dāng)復(fù)位信號為1時，輸出為0
else if(num<31)//分頻
else
begin
num<=0;
reg 2<=~reg_ 2;
end
case(reg_2)
1:squae _out<=255;
0:square_out <=0;
endcase
end
endmodule
控制模式
//triangle_ctrl:三角波控制信號
//sin_ctrl:正弦波控制信號
//square_ctrl:方波控制信號
// triangle:三角波
//sin:正弦波
//square:方波
//wave_out:輸出波形
module control( triangle _ctrl ,sin_ ctrl, square_ctrl,triangle,sin, square,wave_out);
input triangle_ ctrl ,sin _ctrl ,square ctrl;
input[ 7:0] triangle,sin,square;
output[ 7:0] wave_out;
reg[ 7:0] wave_ out;
reg[2:0]sel;
reg[9:0] a,b,c,d,e;
always@( triangle_ctrl or sin_ctrl or square_ctrl or triangle or sin or square)
begin
sel={triangle_ctrl,sin_ctrl,sqpuare_ctrl }; //控制信號
case(sel)
3'b100:wave_out=triangle;
3'b010:wave_out=sin;
3'b001:wave_out=square;
3'b011: //方波和正弦波的線性組合
begin
a= triangle + sin;
wave_out=a[8:1];
end
3'b101: //三角波和方波的線性組合
begin
a = triangle + square;
wave_ out=a[8:1];
end
3 'b110: //三角波和正弦波的線性組合
begin
a= square + sin;
wave_ out=a[8:1];
end
3'b111: //三角波、正弦波和方波的線性組合
begin
a= triangle + square;
b=a + sin;
c=b[9:2];
d=a[9:4];
e=a[9:6];
a=c +d;
b=a +e;
wave_out=b[7:0];
end
defalt:wave_ out=8 'bx;
endcase
end
endmodule
//clk:系統(tǒng)時鐘信號
//reset:復(fù)位信號
//p:頻率調(diào)節(jié)信號,p=系統(tǒng)時鐘頻率/產(chǎn)生頻率/2
module div_ctrl(clk,p,clk_out,reset)
input clk,reset;
input[ 10:0] p ;
output clk_out;
reg clk_ out;
reg temp;
reg [10:0] count ;
always@(posedge clk or posedage reset)
begin
if( reset)clk_out<=0;//復(fù)位信號為1時，輸出為0
else if(temp==0)
begin
count<=p-1;
temp<=1;
end
else if(count==1)
begin
temp<=0;
clk_out<=~clk_out;
end
else
begin
count <= count-1;
end
end
endmodule
module signal_gennerator(clk,reset,k,triangle,sin,square,wave);
input clk,reset;
input[10:0] k;
input triangle,sin,square;
output[7:0] wave;
wire[7:0] triangle_1,sin_1,square_1;
wire clk_1;
div_ctrl U1(.clk(clk),.reset(reset),.p(k),.clk_(clk_1));
control U2(.triangle_ctrl(triangle),.sin_ctrl(sin),.square_ctrl(square),.triangle(triangle_1),
.sin(sin_1),.square(square_1),.wave_out(wave));
triangle U3(.clk(clk_1),.reset(reset),.triangle_out(triangle_1));
sin U4(.clk(clk_1),.reset(reset),.sin_out(sin_1));
square U5(.clk(clk_1),.reset(reset),.square_out(square_1));
endmodule

復(fù)制代碼

ID:275826 · 發(fā)表于 2019-9-7 22:42

還是DDS有效

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基于FPGA的信號發(fā)生器程序

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