74LS161的vhdl實現(xiàn)
1).Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity COurt161 IS
port( clk,CTT,CTP,LD,CR:in std_logic;
D: in std_logic_vector(3 DOWNTO 0);
CQ:out std_logic_vector(3 downto 0);
Co: out std_logic);
end court161;
architecture court161 of court161 is
signal a,b,c: std_logic ;
signal CQI:std_logic_vector(3 downto 0);
begin
a<=CTT and CTP;
b<=(not (CQI(3) and CQI(0)))and LD;
processclk,CTP,LD,CR) begin
if a='1' then
if clk'event and clk='1' then
if b='0' then CQI<=D;
else CQI<=CQI+1;
end if;
end if;
if CQI=9 then c<='1';
else c<='0';
end if;
end if;
if clk'event and clk='1' then Co<=c;
end if;
if CR='0' then CQI<="0000";
end if;
CQ<=CQI;
end process;
end court161;