VHDL語(yǔ)言之運(yùn)算方法的74LS290計(jì)數(shù)器

運(yùn)算方法編寫(xiě)的74ls290計(jì)數(shù)器：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CT290 is
   port(R1,R0,S1,S0,clk:in std_logic;
                 Q:out std_logic_vector(3 downto 0);
                 Co:out std_logic);
end CT290;
architecture cccp of CT290 is
   signal RR,SS:std_logic_vector(1 downto 0);
   signal QI: std_logic_vector(3 downto 0);
   signal C:std_logic;
   begin
     RR<=R1 & R0;SS<=S1 & S0;   
     process(R1,R0,S1,S0,clk,RR,SS)      
        begin
        if clk'event and clk='0' then
           if  QI<9 then  QI<= QI+1;
           else QI<="0000";
           end if;
        end if;
        if    RR="11"     then   QI<="0000";        
        end if;
        if    SS="11"    then    QI<="1001";
        end if;
        if   QI=9   then    C<='1';
        else    C<='0';
        end if;
        if   clk'event   and   clk='0'    then    Co<=C;      
        end if;
      Q<=QI;  
     end process;
end;