半加器的VHDL程序

半加器1

LIBRARY     IEEE;
USE      IEEE.STD_LOGIC_1164.ALL;
ENTITY     halfadder      IS
  PORT (A,B:IN STD_LOGIC;
        Co: out STD_LOGIC;
        S:  out STD_LOGIC);
end      halfadder;
ARCHITECTURE    rtl    OF      halfadder     IS
      BEGIN
     S <=A XOR B;
     Co <=A AND B;
  END rtl;