VHDL_優(yōu)先編碼器程序

ENTITY prior_encoder IS
PORT(i0,i1,i2,i3:IN BIT;
           y0,y1:OUT BIT);
END prior_encoder;
ARCHITECTURE behavioral OF prior_encoder IS
BEGIN
cale:PROCESS(i0,i1,i2,i3)
     VARIABLE temp:std_logic_vector(1 downto 0);
BEGIN
 IF i3='0' THEN temp:="11";
 ELSEIF i2='0' THEN temp:="10";
 ELSEIF i2='0' THEN temp:="01";
 ELSEIF i3='0' THEN temp:="00";
END IF;
y0<=temp(0);
y1<=temp(1);
END PROCESS;
END behavioral;