`define N 23
module audio_mix_add_24bit (
input clk ,
input rst ,
input [`N:0] audio_a ,
input [`N:0] audio_b ,
output reg [`N:0] mixed_audio_out
);
parameter NEG_ADD_MAX = 24'hFF_FFFF;
reg [24:0] mixed_audio;
wire [23:0] neg_add_a;
wire [23:0] neg_add_b;
wire [23:0] neg_add;
////////////////////////////////////////////////////////////
////////////////// 補碼的相加運算 ///////////////////////////
////////////////////////////////////////////////////////////
assign neg_add_a = NEG_ADD_MAX - audio_a + 1'b1;
assign neg_add_b = NEG_ADD_MAX - audio_b + 1'b1;
always @( posedge clk , negedge rst )
if( !rst )
mixed_audio <= 25'h0;
else if( !audio_a[23] & !audio_b[23] )
begin
mixed_audio[23:0] <= audio_a[23:0] + audio_b[23:0];
mixed_audio[24] <= 1'b0;
end
else if( audio_a[23] & audio_b[23] )
begin
mixed_audio[23:0] <= neg_add_a + neg_add_b; //TT NEG_ADD_MAX - neg_add_anbn[23:1] + 1'b1;
mixed_audio[24] <= 1'b1;
end
else if( !audio_a[23] & audio_b[23] )
if( audio_a[23:0] >= neg_add_b )
begin
mixed_audio[23:0] <= audio_a[23:0] - neg_add_b;
mixed_audio[24] <= 1'b0;
end
else
begin
mixed_audio[23:0] <= neg_add_b - audio_a; //TT NEG_ADD_MAX - neg_add_apbn[23:1] + 1'b1;
mixed_audio[24] <= 1'b1;
end
else if( audio_a[23] & !audio_b[23] )
if( neg_add_a >= audio_b[22:0] )
begin
mixed_audio[23:0] <= neg_add_a - audio_b; //TT NEG_ADD_MAX - neg_add_anbp[23:1] + 1'b1;
mixed_audio[24] <= 1'b1;
end
else
begin
mixed_audio[23:0] <= audio_b[23:0] - neg_add_a;
mixed_audio[24] <= 1'b0;
end
always @( posedge clk , negedge rst )
if( !rst )
mixed_audio_out <= 24'h0;
else if( !mixed_audio[24] )
mixed_audio_out <= { mixed_audio[24], mixed_audio[23:1] };
else
mixed_audio_out <= NEG_ADD_MAX - mixed_audio[23:1] + 1'b1 ;
endmodule
