MSP430F5529單片機(jī)的P1.7、P2.2 io口中斷和頻率設(shè)置程序：
#include "msp430F5529.h"
#define P15_H (P1IN & BIT5);
#define P15_L (P1OUT & (~BIT5));
int tt=0,temp,kk,i;
void delay(int ns)
{
int kk;
while(ns--)
for(kk=0;kk<120;kk++);
}
//******A/D轉(zhuǎn)換函數(shù)設(shè)置*****//
void adc1()
{
P1SEL |=BIT6; //轉(zhuǎn)換模擬信號(hào)從P1.6輸入，內(nèi)部集成了轉(zhuǎn)換模塊
ADC12CTL0 =ADC12ON + ADC12SHT02 + ADC12MSC;
ADC12CTL1 =ADC12SHP + ADC12CONSEQ_2;
ADC12MCTL0=ADC12SREF_0+ADC12INCH_6;
ADC12CTL0 |=ADC12ENC;
//////一次轉(zhuǎn)換結(jié)束后產(chǎn)生轉(zhuǎn)換中斷調(diào)用ADC中斷函數(shù)////
}
void MainFre24M(void)
{
UCSCTL3 |=SELREF__REFOCLK;
__bis_SR_register(SCG0); //disable the FLL control loop
UCSCTL0=0X0000;// //Set lowest possible DCOx,MODxSCG0
UCSCTL1=DCORSEL_6; //Select DCO range 24MHz opreation
//DCORSEL_x，其中x可選3、4、5、6、7
UCSCTL3=FLLD_0+731; //Set DCO Multiplier for 24MHz
//(N+1)*FLLRef=Fdco
//(731+1)*32768=24MHz
//Set FLL DIV =fDCOCLK/2
__bis_SR_register(SCG0); //Enable the FLL control loopSCG0
UCSCTL4 |=SELA__DCOCLK+SELS__XT1CLK+SELM__DCOCLK;//MCLK Source select
UCSCTL5 |=DIVPA_2; //ACLK output divide
UCSCTL6 |=XT1DRIVE_3+XCAP_0; //XT1 cap
}
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
MainFre24M();
UCSCTL3=FLLD_0+731;
UCSCTL1=DCORSEL_7;
P1REN |=BIT7;
P1OUT |=BIT7;
P1IE |=BIT7;
P1IES|=BIT7;
P1IFG&=~BIT7;
P2REN |=BIT2;
P2OUT |=BIT2;
P2IE |=BIT2;
P2IES|=BIT2;
P2IFG&=~BIT2;
__enable_interrupt();
P1DIR |= 0x3f;
P1DS |= 0x3f;
while(1)
{
UCSCTL1=DCORSEL_3;
P1OUT |=BIT5;
delay(1000);
P1OUT &=~BIT5;
delay(1000);
}
}
#pragma vector=PORT1_VECTOR
__interrupt void PORT17ISR(void)
{
int i;
UCSCTL1=DCORSEL_7;
UCSCTL3=FLLD_7+730;
for(i=0;i<40;i++)
{
P1OUT |=BIT0;
delay(1000);
P1OUT &= ~BIT0;
delay(1000);
}
P1IFG &=~BIT7;
}
#pragma vector=PORT2_VECTOR
__interrupt void PORT22ISR(void)
{
int i;
UCSCTL1=DCORSEL_7;
UCSCTL3=FLLD_7+730;
for(i=0;i<40;i++)
{
P1OUT |=BIT3;
delay(1000);
P1OUT &= ~BIT3;
delay(1000);
}
P2IFG &=~BIT2;
}